Principal Test Engineer/DFT Architect

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified checked Jun 7, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$111,944 U.S. median for this role

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Data From the posting source

Seniority

Staff Plus From the posting source

Schedule

Shift type

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Weekend work

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Application

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Assessment

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Deadline

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Where they hire

State eligibility is not yet verified.

About this role

Principal Test Engineer/DFT Architect Austin, TEXAS, United States Company Description: The Principal Test / DFT Architect will define testability and production test strategy for advanced semiconductor products from concept through production release. This role bridges ATE test architecture, DFT, circuit design, product engineering, validation, quality, operations, and manufacturing to ensure products are designed for high-quality, cost-effective, scalable production test. The ideal candidate has deep semiconductor ATE test experience, strong knowledge of analog, mixed-signal, digital, and power-management IC testing, and enough circuit design understanding to influence observability, controllability, trim/calibration strategy, test muxing, embedded monitors, diagnostic coverage, and test strategy before tape-out. This is a senior technical leadership role for an individual contributor who can set strategy, influence design and engineering teams, mentor engineers, and establish reusable test and DFT methodologies across product families. Job Description: Test and DFT Architecture · Define product-level test and DFT strategy, including wafer probe, final test, characterization, qualification, GRR, production test flow, and cost-of-test targets. · Partner with design, systems, validation, product engineering, test engineering, quality, operations, and manufacturing teams to define DFT requirements early in the lifecycle. · Drive requirements for test muxes, scan/debug access, analog observability, digital controllability, embedded monitors, BIST where applicable, trim/calibration access, fuse/NVM test modes, and diagnostic hooks. · Review schematics, architecture documents, specifications, register maps, and test-mode plans to identify testability gaps before design freeze. · Establish reusable DFT and test-access standards for power, analog, mixed-signal, and digitally assisted products. ATE and Production Test Strategy · Define ATE platform strategy,

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