Principal DFT Engineer

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified

Salary

$155K-$193K From the posting source checked Jun 20, 2026

401(k) match

Not verified

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Market context

U.S. role benchmark (BLS OEWS)

$55,390 U.S. median for this role

Projected growth (BLS Employment Projections)

-0.1% - Decline

214% above the BLS role benchmark for teaching and education aggregate.

Posted salary is far from this role benchmark; treat it as low confidence.

Matched to SOC 25-2021 - Teaching and Education aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Teaching Education From the posting source checked Jun 20, 2026

Seniority

Principal From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Principal DFT Engineer Carlsbad, CA, US; Irvine, CA, US Responsibilities MaxLinear is seeking a Principal DFT (Design For Test) Engineer to join our team. In this role, you will focus on the following: Lead DFT and implementation of DFT techniques on System on Chip (SOC) Define DFT architecture, RTL coding, simulation and verification, chip testing, and supporting Automatic Test Equipment (ATE) issues Develop DFT methodologies that reduce test cost, increase product quality, and enhance yield learning on leading edge process technologies Generate DFT pattern, coverage analysis, and debug as well as running and debugging gate level simulations Assist Test Engineers to bring up ATPG and MBIST pattern on the ATE Resolve issues during characterization Qualifications Strong understanding of Fault modeling, Scan compression, and Memory testing techniques Experience in all aspects of DFT flow, including DC/AC scan, ATPG, JTAG/boundary SCAN, memory BIST, high speed interface test Understanding of the entire ASIC design flow: logic design, Verilog/VHDL verification, synthesis, timing, and backend Proven record of supporting a large volume of commercial SOC shipments Excellent analytical and debugging skills and the ability to proactively resolve issues Must be able to work autonomously and guide others based on changing priorities Proven ability to thrive on, learn, and adapt to new methodologies and technologies Excellent oral and written communication skills BS in Electrical Engineering or related + 9 years of experience, or MS + 7 years

Read the full description at careersus-maxlinear.icims.com. FewerJobs shows a preview and links to the original posting.