Principal Analog Circuit Design Engineer - SerDes

Verified benefits

Parental leave

12 weeks

Non-birth-parent leave

12 weeks

Verified

Yes last checked unknown

Salary

$221K-$312K

401(k) match

Not verified

Market context

Median wage (BLS OEWS)

$116,543 national median

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

129% above the BLS national median for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Where they hire

State eligibility is not yet verified.

About this role

Principal Analog Circuit Design Engineer - SerDes 3 Locations Principal Analog Circuit Design Engineer - SerDes /job/US-California-Santa-Clara/Principal-Analog-Circuit-Design-Engineer---SerDes_JR0283655 3 Locations Posted 6 Days Ago

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