Technology Lead- Memory Layout

Benefits

Parental leave

Not verified

Non-birth-parent leave

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Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

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Salary

$90K-$136K not verified - source not recorded; timestamp not recorded

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Market context

U.S. role benchmark (BLS OEWS)

$102,662 U.S. median for this role

Projected growth (BLS Employment Projections)

+5.4% - Faster than average

U.S. benchmark only; posted salary is not compared across countries or currencies.

Matched to SOC 11-1021 - Product Management aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

Shift type

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Weekend work

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Application

Cover letter

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Assessment

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Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Technology Lead- Memory Layout Infosys is hiring Memory Team Layout. You will work along our Registers and Memory Arrays and Memory data path layout and design engineers .Based on the schematic shared you should be able to take it forward and collaborate with circuit team etc to create best layout possible. Required Qualifications: - Candidate must be located within commuting distance of Vancouver BC, Canada or be willing to relocate to the area. This position may require travel in Canada. - Bachelor's degree or foreign equivalent required from an accredited institution. Will also consider three years of progressive experience in the specialty in lieu of every year of education. - At least 4 years of Information Technology experience. - Candidates authorized to work for any employer in the Canada without employer-based visa sponsorship are welcome to apply. Infosys is unable to provide immigration sponsorship for this role at this time. Required Skills - Minimum Qualifications 5+ years of experience in Compiler/Custom Memory Layout design. - Memory Leafcell layout library design from scratch including top level integration. - Good knowledge on diAerent types of memory architectures. - Good knowledge in optimized layout design for better performance. - Sound knowledge & hands on experience in Finfet technology, layout design and DRC limitations. - 3nm, 5 nm exposure required Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions. - Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow. The job may also entail sitting as well as

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