Senior ASIC Design Verification Engineer

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified last checked Jun 13, 2026

Salary

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401(k) match

Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

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Market context

U.S. role benchmark (BLS OEWS)

$111,944 U.S. median for this role

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

Shift type

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Weekend work

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Application

Cover letter

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Assessment

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Deadline

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Where they hire

State eligibility is not yet verified.

About this role

Senior ASIC Design Verification Engineer Bengaluru, Karnātaka, India Join our team as a Senior ASIC Design Verification Engineer and lead advanced verification for cutting-edge ASICs. Drive innovation using SystemVerilog, UVM, and simulation tools. Collaborate with top engineers, own end-to-end verification, and shape the future of hardware validation. Grow your career with HPE's global technology team.

Read the full description at hpe.wd5.myworkdayjobs.com. FewerJobs shows a source-linked preview and links to the original posting.