Silicon Physical Design CAD Engineer
Google - New Taipei, Banqiao District, New Taipei City, Taiwan; +1 more
Posted Jun 1, 2026
Benefits
- Parental leave
- 18 weeks Verified - employer source source checked May 7, 2026
- Non-birth-parent leave
- 18 weeks Verified - employer source source checked May 7, 2026
- Family-building benefits
-
- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
- Not verified
- Relocation assistance
- Not verified
- Childcare support
- Not verified
- Learning budget
- Not verified
- Verification
- Source-linked checked May 7, 2026
- Salary
- Not verified
- 401(k) match
- Reported from DOL Form 5500 industry filing (not employer-specific)
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Market context
- U.S. role benchmark (BLS OEWS)
- $66,396 U.S. median for this role
- Projected growth (BLS Employment Projections)
- +3.5% - Average
Matched to SOC 27-1024 - Design aggregate by role bucket.
Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.
Role
Schedule
- Shift type
- Not verified
- Weekend work
- Not verified
Company
- Equity
- Offered Verified - SEC 10-K source checked Jun 20, 2026
Application
- Cover letter
- Not verified
- Assessment
- Not verified
- Deadline
- Not stated
Where they hire
State eligibility is not yet verified.
About this role
Silicon Physical Design CAD Engineer New Taipei, Banqiao District, New Taipei City, Taiwan; +1 more Be part of a various team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Co-work with project team for a more efficient and effective flow execution and results review mechanism in PDV field. Co-work with the methodology team to define Physical Design Verification (PDV) flow requirements for technology nodes Design Rule Check (DRC), Layout Versus Schematic (LVS), and Programmable Electrical Rule Check (PERC) checks. Import new features, improve job efficiency, and maintain a stable flow in PDV analysis to meet technology and project needs. Provide flow usage and execution support with documentation, training and troubleshooting. Minimum qualifications: Bachelor's degree in Electrical Engineering, a similar field, or equivalent practical experience. 4 years of experience in scripting languages such as Perl, TCL, Shell, or Python. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a similar field. 5 years of experience
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