Senior Silicon Diagnostics Engineer

Benefits

Parental leave

18 weeks From the posting source checked Jun 20, 2026

Non-birth-parent leave

18 weeks From the posting source checked Jun 20, 2026

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Source-linked checked May 7, 2026

Salary

Not verified

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Senior From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Senior Silicon Diagnostics Engineer Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Silicon Diagnosis and Defect Isolation: Perform post-silicon electrical and physical fault isolation using production test results (e.g., error logs, flop mapping, and software-based diagnosis) to narrow down the cone of logic. Methodology Development: Develop, deploy, and automate volume diagnosis and data analysis flows. Generate and apply specialized diagnosis patterns for Soft-Defect-Location (SDL) or Laser-Voltage-Imaging (LVI). Cross-Functional Collaboration: Partner with Design, DFX, Verification, and Test teams to define requirements for highly diagnosable designs and to build layout databases for diagnosis and cross-probing. EFA and Root Cause Analysis: Define and execute Electrical Failure Analysis (EFA) workflows to root-cause yield issues, qualification failures, and customer returns. ATE and Pattern Debug: Lead silicon bring-up, debug, and validation of DFT features on Automated Test Equipment (ATE), debugging ATPG patterns, Compressed ATPG patterns, MBIST, and JTAG related issues. Minimum qualifications: Bachelor's degree in Electrical Engineering,

Read the full description at www.google.com. FewerJobs shows a preview and links to the original posting.