CPU Design Verification Engineer

Benefits

Parental leave

18 weeks From the posting source

Non-birth-parent leave

18 weeks From the posting source

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Source-linked checked May 7, 2026

Salary

Not verified

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$111,944 U.S. median for this role

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Data From the posting source

Seniority

Mid From the posting source

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Equity

Offered Verified - SEC 10-K source

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

CPU Design Verification Engineer New Taipei, Banqiao District, New Taipei City, Taiwan; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Design verification for future CPU developments. Build functional verification infrastructure, the infrastructure will include unit, multi-unit, core, and subsystem level verification environments. Produce diagnostic code repositories that enable production of CPU's. Verify and validate performance for both pre-silicon and post-silicon. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 4 years of experience with verification methodologies and languages such as Universal Verification Methodology (UVM) and SystemVerilog. Experience developing and maintaining verification test benches, test cases, and test environments. Preferred qualifications: Master's degree in Electrical Engineering, Computer Science, or a related field. Experience with Universal Verification Methodology, SystemVerilog, or other scripting languages such as Python, Perl, Shell, Bash, etc. Experience with ARM Instruction Set Architecture. Knowledge of general purpose operating systems such as Linux

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