ASIC Design for Testability Engineer, Silicon

Benefits

Parental leave

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Source-linked last checked May 7, 2026

Salary

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401(k) match

Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked May 7, 2026.

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About this role

ASIC Design for Testability Engineer, Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Work with a team of DFT engineers, working with RTL, Physical Designer Engineers, SOC DFT and Product Engineering team. Work on Subsystem level DFT SCAN, MBIST Architecture with multiple voltage, power domains. Write basic to complex scripts to automate the DFT flow. Develop tests that can be used for Production in the ATE flow. Work with the members of the DFT team to deliver overall deliverables for 2 or more complex Subsystems in a SoC. Minimum qualifications: Bachelor's degree in Building Engineering, Electrical and Electronics Engineering, Controls, IT, or equivalent practical experience. 4 years of experience in DFT/DFD flows and methodologies. Experience with Scan insertion, Automatic Test Pattern Generation (ATPG), Gate Level Simulations and Silicon Debug, Low Power designs, Built-In Self-Test (BIST), Joint Test Action Group (JTAG), Internal JTAG (IJTAG) tools and flow. Experience with DFT EDA

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