Lead FPGA Engineer

Verified benefits

Parental leave

4 weeks source

Non-birth-parent leave

4 weeks

Verified

Yes last checked 2026-05-07

Salary

Not disclosed

401(k) match

Not verified

Market context

Median wage (BLS OEWS)

$116,543 national median

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Where they hire

State eligibility is not yet verified.

About this role

Lead FPGA Engineer 2 Locations Date Posted: 2026-02-03 Country: United Kingdom Location: GB-PLY-PLYMOUTH-C ~ Clittaford Rd Southway ~ BLDG C Position Role Type: Unspecified At Collins Aerospace, precision and reliability

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