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Platform Validation Engineer

Etched - San Jose, CA, United States

Posted Feb 3, 2026

Benefits

Parental leave
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Non-birth-parent leave
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Family-building benefits
  • Fertility benefits: Not verified
  • Adoption assistance: Not verified
  • Surrogacy assistance: Not verified
Mental health support
Offered From the posting source checked Jun 20, 2026
Relocation assistance
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Childcare support
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Learning budget
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Verification
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Salary
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401(k) match
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Market context

U.S. role benchmark (BLS OEWS)
$116,543 U.S. median for this role
Projected growth (BLS Employment Projections)
+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function
Engineering From the posting source checked Jun 20, 2026
Seniority
Mid From the posting source checked Jun 20, 2026

Schedule

Shift type
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Weekend work
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Application

Cover letter
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Assessment
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Deadline
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Where they hire

State eligibility is not yet verified.

About this role

Platform Validation Engineer San Jose, CA, United States About Etched Etched is building the world's first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary We are seeking an experienced and motivated Platform Validation Engineer to validate system hardware and printed circuit board (PCB) functionality and ensure robust power and signal margins across all interfaces. In this role, you will collect and analyze lab data to validate hardware performance, support post-silicon characterization, and ensure reliable operation across multiple subsystems, including PCIe and I2C. Key Responsibilities - Perform system hardware and PCB functional verification to ensure all features meet design specifications, including validation of power and signal integrity margins - Collect and analyze lab data to verify power delivery, signal integrity, and overall system robustness - Support post-silicon validation by identifying key performance metrics and conducting PVT, power, and thermal characterization - Evaluate PCIe performance, including signal integrity, eye opening measurements (EOM), and bit error rate (BER), to ensure adequate operating margins - Identify hardware issues, perform root cause analysis, and drive issues to resolution in collaboration with cross-functional teams - Design and execute DOE

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