Technical Leader DFT & STA

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Not verified last checked Jun 13, 2026

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401(k) match

Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

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About this role

Technical Leader DFT & STA Armenia Meet the team Join the Silicon One Team at Cisco, a group at the forefront of developing Cisco's groundbreaking silicon architecture. We are a collaborative unit focused on pushing the boundaries of ASIC design for advanced process nodes. As part of our team, you will contribute to defining innovative Physical Design methodologies and creating robust flows essential for developing our complex chips. You will also have the opportunity to work hands-on with the Physical Design of intricate chip partitions. Your Impact You are a detail-oriented DFT Timing Engineer with strong analytical skills and a deep understanding of timing constraints, such as clock groups, various exceptions, clock exclusivity. You will collaborate effectively with cross-functional teams, communicate complex timing data clearly. Responsibilities will include: Developing timing constraints at block, sub-chip, and full-chip levels in test modes, performing quality checks such as duplicated constraints, promotion/demotion between block and top level SDCs. Check timing for unconstrained endpoints, no clock, etc. Your role may include SDC validation, CDC delay check, and SDC flow development. Developing methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to ensure progress and accuracy. Minimum Qualifications Bachelor's degree in electrical or computer engineering (or other equivalent field) with 8+ years of related work experience. Experience with block/full chip SDC development in test modes (scan shift, scan capture, atpg capture modes). Expertise in Static Timing Analysis and prior working experience with STA tools like PrimeTime. Programming skills in

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