Chip Level STA Engineer

Benefits

Parental leave

Not verified

Non-birth-parent leave

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Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified checked Jun 13, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Chip Level STA Engineer Armenia Meet the Team Join Cisco's ASIC Physical Design Team, where we ensure the highest quality in full-chip timing closure and circuit performance to guarantee a successful tape-out. We bridge the gap between design and reality by collaborating across block implementation, flow, SDC, EMIR, and IP/tool vendor teams to drive silicon excellence. As a tight-knit group of highly skilled engineers, we foster a collaborative environment where innovation meets precision. Together, we are building the foundation for the future of connectivity, driving advancements in power, performance, and reliability with every project. This is your opportunity to shape the technology that connects the world while working alongside a team that values mentorship and celebrates technical success. Your Impact Drive Cisco's silicon innovation by ensuring high-performance timing closure and rigorous sign-off for our next-generation chips to guarantee a successful tape-out. Analyze full-chip timing and design rule violations to identify root causes and implement effective solutions that maintain design integrity. Develop robust timing closure methodologies for block and top-level designs to streamline development and improve efficiency. Collaborate closely with implementation teams to ensure smooth ECO execution and seamless design handoffs. Evaluate complex clocking structures and timing constraints to guarantee that all silicon solutions meet stringent performance targets. Minimum qualifications Bachelor's or Master's degree in Electrical Engineering or Computer Science. Minimum of 3 years of hands-on experience in ASIC design and verification. Proven experience working with deep submicron CMOS technologies. Comprehensive knowledge of the full design cycle from RTL to GDSII.

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