Full-Chip Physical Design Engineer

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Not verified last checked Jun 13, 2026

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401(k) match

Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

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About this role

Full-Chip Physical Design Engineer Armenia Meet the Team Step into Cisco's ASIC Physical Design Team, where innovation meets collaboration. As a group of highly skilled engineers, we're redefining what's possible in silicon technology. Our mission is to drive the future of chip design, managing full-chip physical implementation from RTL to GDSII and beyond. Working hand-in-hand with Front-End teams, we transform cutting-edge designs into industry-leading silicon solutions. Together, we're building the foundation for the future of connectivity, driving advancements in power, performance, and reliability with every project. Your Impact Drive Cisco's silicon innovation by creating breakthrough solutions that blend hardware and software to empower people worldwide. Execute top-level RTL to GDSII implementation and signoff to ensure the delivery of high-quality, reliable silicon. Perform critical physical design tasks, including gate-level netlist synthesis, floorplanning, and routing, while applying advanced Clock Tree Architectures like Mesh and H-Tree. Optimize designs to achieve industry-leading power, performance, and area (PPA) metrics while maintaining design integrity through formal verification. Collaborate with multi-functional teams to accelerate design processes and deliver impactful technology that shapes the future of connectivity. Minimum Qualifications Bachelor's or Master's degree in Electrical Engineering or Computer Science. Minimum of 3 years of experience in ASIC design and verification. Experience in deep submicron CMOS technologies. Comprehensive knowledge of the full design cycle from RTL to GDSII. Preferred Qualifications Experience in RTL2GDS flow, floorplanning, and power planning. Proficiency in PnR tools such as Synopsys or Cadence. Strong scripting skills for automation and efficiency improvements. Experience with chip-level design

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