Senior STA Timing Engineer
Cisco - Armenia
Posted May 21, 2026
Benefits
- Parental leave
- Not verified
- Non-birth-parent leave
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- Family-building benefits
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- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
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- Relocation assistance
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- Childcare support
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- Learning budget
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- Verification
- Not verified last checked Jun 13, 2026
- Salary
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- 401(k) match
- Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.
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Schedule
- Shift type
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- Weekend work
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Application
- Cover letter
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- Assessment
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- Deadline
- Not stated
Where they hire
State eligibility is not yet verified.
About this role
Senior STA Timing Engineer Armenia Meet the team Join our dynamic Test Timing Engineering team, a group of passionate experts dedicated to ensuring robust and accurate timing constraints for advanced chip designs. Our work is critical to the success of the broader silicon design process, enabling efficient test and verification of complex integrated circuits. The team is mid-sized, blending seasoned engineers with fresh perspectives, fostering a collaborative and supportive environment. You'll find an atmosphere of innovation, continuous learning, and strong cross-functional collaboration, all driven by a commitment to technical excellence. If you thrive on solving challenging problems and making a tangible impact on product quality, you'll feel right at home here. Your impact As a Test Timing Engineer, you will play a pivotal role in developing and validating timing constraints that ensure the accuracy and reliability of advanced chip designs. Own the creation and validation of timing constraints at block, sub-chip, and full-chip levels in various test modes. Perform quality checks, including identifying duplicated constraints and verifying unconstrained endpoints, to drive robust timing analysis. Develop and enhance methodologies, guidelines, and checklists to streamline static timing analysis (STA) workflows. Collaborate with cross-functional teams to resolve timing and design flow issues, accelerating project execution. Implement and maintain SDC flows and validation processes to ensure compliance and accuracy across all design stages. Minimum qualifications Bachelor's degree in electrical or computer engineering (or equivalent field) with 8+ years of relevant work experience or Master's degree in electrical or computer engineering (or equivalent) with 6+
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Apply link verified; last checked Jun 13, 2026.
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