Senior Physical Design Engineer - Signoff Methodology

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified checked Jun 13, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Senior From the posting source checked Jun 20, 2026

Work mode

Hybrid From the posting source checked Jun 20, 2026

In-office days

2 days From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

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Company

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

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Assessment

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Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Senior Physical Design Engineer - Signoff Methodology Armenia This is a hybrid role with four days per week at Cisco's Yerevan office. Meet the Team You'll be joining our CAD Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This team is a critical part of the group leading the development of high-quality VLSI designs and supports the creation of advanced silicon. Our design center brings together all silicon hardware and software development fields, encouraging collaboration and technical excellence. Your Impact As part of our team, you'll help develop and improve flows for all signoff disciplines and contribute to the evolution of implementation tool flows. You'll play a key role in enabling the delivery of high-performance, large-scale, and complex devices that push the boundaries of what's possible in chip design. Develop and refine backend methodologies and flows from RTL to GDS, supporting high-quality VLSI design. Contribute to the advancement of all signoff flows, including physical synthesis, place and route, power optimization, timing closure, and physical closure. Collaborate with engineering teams to support and enhance implementation tool flows. Work with advanced silicon technologies and processes to deliver complex and reliable devices. Minimum Requirements 5+ years of experience as a CAD Physical Design Engineer with PnR and STA or as a Design Engineer with strong backend design experience. B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering, or a related field. Strong understanding of STA flows. Familiarity with PnR,

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