Senior PCB ECAD engineer

Benefits

Parental leave

Not verified

Non-birth-parent leave

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Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified checked Jun 13, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Senior From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Senior PCB ECAD engineer Bangalore, India Meet the Team We are part of the Cisco Hardware Engineering group, dedicated to developing next-generation technology and hardware products. Our team focuses on the end-to-end development of high-complexity Printed Circuit Boards (PCBs) that adhere to IEEE standards and industry best practices. We prioritize user experience and technical excellence, ensuring our hardware is robust, scalable, and manufacturable. You will work in a high-impact environment, driving innovation in PCB design and collaborating with global cross-functional teams to bring cutting-edge products from conception to fabrication. Your Impact Execute complex PCB designs involving 30+ layers and advanced technologies such as HDI (High-Density Interconnect), Fine Pitch Pin Fields, and High IO counts. Drive resolution of critical issues by working closely with Signal Integrity (SI), Mechanical (MCAD), and Manufacturing Engineers. Champion and implement new ECAD design methodologies and point tools (csh, Allegro scripts) to improve local tool performance and productivity. Provide guidance to junior ECAD engineers and train peer groups on ECAD processes and best practices. Apply Signal Integrity rules, EMC, Safety, and DFM (Design for Manufacturability) guidelines to ensure first-pass success. Participate in cross-functional meetings with CM (Contract Manufacturers) and Fabrication vendors to incorporate feedback into designs. Minimum Qualifications Requires a BTech/MTech in EE/EC or a related field with 8+ years of experience in advanced technology PCB design. Proven ability to design high-complexity PCBs (30+ layers) using advanced technologies (HDI, Fine Pitch). Strong hands-on experience with ECAD tools (specifically Cadence Allegro) and scripting (csh, Allegro scripts). Deep understanding

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