ASIC Technical Leader- DFT

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401(k) match

Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

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About this role

ASIC Technical Leader- DFT San Jose, California, US The application window is expected to close on: 05/08/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Meet the Team: You will be in the Silicon One development organization as an ASIC Implementation Technical Lead with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities. Key Contributions: Manages the definition, architecture and design of high performance ASICs Owns applications or multiple complex functional areas Oversees reusable code and its applications Creates re-usable code that promotes efficiencies in new ways Defines verification strategies Coordinates with appropriate stakeholders to integrate into PD and DV flows Owns infrastructure and testing environmens Leads and designs the building blocks of multiple channels Applies and drives the design methodology from conception to production Influences and collaborates with teams to ensure specifications and requirements are met Leads technical expertise of a physical design function Interfaces with vendors and design leads on full chip timing closure, PI, and PV Owns the full electrical planning and specifications of electrical interfaces Develops

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