ASIC Physical Design Engineer

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified checked Jun 13, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Work mode

Hybrid From the posting source checked Jun 20, 2026

In-office days

2 days From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

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Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

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Assessment

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Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

ASIC Physical Design Engineer Armenia This is a hybrid role with four days per week at Cisco's Yerevan office. Meet the Team Our team specializes in macro-level RTL-to-GDSII physical implementation and signoff, collaborating closely with Front-End teams to ensure optimal results. We are dedicated to delivering complex SoC and block-level projects through technical excellence and teamwork. The team is composed of highly experienced professionals who value collaboration and high standards in physical design. Your Impact Lead macro-level RTL-to-GDSII physical implementation and signoff. Collaborate with Front-End teams to translate architecture into optimal physical design. Perform synthesis, floorplanning, placement, Clock Tree Synthesis (CTS), and routing. Optimize power, performance, and area (PPA) while maintaining design correctness through formal verification. Execute static timing analysis (STA), physical verification, formal checks, and signoff closure to ensure reliable, high-quality silicon. Analyze and resolve Electromigration (EM) and IR-drop issues to meet reliability and performance signoff targets. Minimum Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field. 5+ years of hands-on experience in ASIC design and physical implementation. Proven track record in ASIC physical design and verification preferably in complex SoC or block-level projects. Deep knowledge of block-level synthesis, place-and-route (PnR), and timing closure. Experience with industry-standard PnR and signoff tools (e.g., Synopsys, Cadence). Preferred Qualifications Broad understanding of physical design methodologies, integration, and implementation flows. Experience in physical verification (LVS, DRC) and signoff processes. Familiarity with physical design EDA toolchains and end-to-end workflows. Advanced expertise in STA, timing closure, and constraint management. Proficiency

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