ASIC Engineer - SDC

Benefits

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Not verified last checked Jun 13, 2026

Salary

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401(k) match

Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

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About this role

ASIC Engineer - SDC San Jose, California, US The application window is expected to close on: Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . This role requires being onsite in San Jose, CA at least 4 days/week Meet the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and café, social interest groups, and philanthropy), with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact Own and develop full-chip timing constraints (SDC) across functional and test modes for complex networking SoCs. Drive Static Timing Analysis (STA) and partner with RTL, physical design, and DFT teams to resolve timing issues across the design hierarchy. Partner with RTL designers to achieve timing convergence through constraint development and timing-driven RTL improvements. Define and maintain clocking architectures and constraint models, including clock groups, timing exceptions, and clock exclusivity. Integrate and validate timing constraints from third-party IP vendors within the full-chip SoC timing environment. Develop and review block-level SDCs and clocking architectures, ensuring constraint correctness and alignment across the design hierarchy. Contribute to timing closure and silicon readiness across multiple modes, corners, and operating conditions. Minimum Qualifications Bachelor's degree in Electrical or

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