ASIC Engineer - SDC

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified checked Jun 13, 2026

Salary

$165K-$241K From the posting source checked Jun 20, 2026

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

74% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Work mode

Onsite From the posting source checked Jun 20, 2026

In-office days

5 days From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Mar 12, 2026 From the posting source checked Jun 20, 2026

Where they hire

State eligibility is not yet verified.

About this role

ASIC Engineer - SDC San Jose, California, US The application window is expected to close on: Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . This role requires being onsite in San Jose, CA at least 4 days/week Meet the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and café, social interest groups, and philanthropy), with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact Own and develop full-chip timing constraints (SDC) across functional and test modes for complex networking SoCs. Drive Static Timing Analysis (STA) and partner with RTL, physical design, and DFT teams to resolve timing issues across the design hierarchy. Partner with RTL designers to achieve timing convergence through constraint development and timing-driven RTL improvements. Define and maintain clocking architectures and constraint models, including clock groups, timing exceptions, and clock exclusivity. Integrate and validate timing constraints from third-party IP vendors within the full-chip SoC timing environment. Develop and review block-level SDCs and clocking architectures, ensuring constraint correctness and alignment across the design hierarchy. Contribute to timing closure and silicon readiness across multiple modes, corners, and operating conditions. Minimum Qualifications Bachelor's degree in Electrical or

Read the full description at cisco.wd5.myworkdayjobs.com. FewerJobs shows a preview and links to the original posting.