ASIC Engineer Internship (Armenia)
Cisco - Armenia
Posted May 12, 2026
Benefits
- Parental leave
- Not verified
- Non-birth-parent leave
- Not verified
- Family-building benefits
-
- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
- Not verified
- Relocation assistance
- Not verified
- Childcare support
- Not verified
- Learning budget
- Not verified
- Verification
- Not verified last checked Jun 13, 2026
- Salary
- Not verified
- 401(k) match
- Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.
Was this benefit information wrong? Tell us.
Schedule
- Shift type
- Not verified
- Weekend work
- Not verified
Application
- Cover letter
- Not verified
- Assessment
- Not verified
- Deadline
- Not stated
Where they hire
State eligibility is not yet verified.
About this role
ASIC Engineer Internship (Armenia) Armenia Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. Meet the Team Join our specialized ASIC implementation team where we bridge the gap between architectural design and physical silicon reality. Our team provides a structured, mentorship-driven environment focused on block-level and top-level physical implementation, timing closure, and physical verification. We work at the heart of Cisco's hardware innovation, ensuring that our next-generation semiconductor technologies are reliable, efficient, and high-performing. You will collaborate with experienced engineers who are passionate about teaching and pushing the boundaries of VLSI technology. This is an exciting opportunity to gain hands-on experience with industry-standard tools while contributing to the hardware that powers the global internet. Your Impact Support physical design tasks including floorplanning, placement, and routing to ensure efficient ASIC implementation. Participate in Static Timing Analysis (STA) and timing closure activities to meet critical design performance specifications. Assist in IR Drop and EMIR analysis to maintain power integrity and long-term reliability of the hardware. Perform physical verification checks such as DRC and LVS to guarantee manufacturing readiness and design rule compliance. Prepare technical documentation and reports to communicate progress and findings to the broader engineering team. Minimum Qualifications • Currently enrolled in a Bachelor's or Master's program in Microelectronics, VLSI, Electrical Engineering, or a related field. • Strong academic foundation
Read the full description at cisco.wd5.myworkdayjobs.com. FewerJobs shows a source-linked preview and links to the original posting.
Apply link verified; last checked Jun 13, 2026.
What verified means
Verified means a displayed claim has a recorded source field, a source URL when available, and a timestamp showing when FewerJobs checked or enriched the evidence.
Related jobs
-
ASIC Design Verification Engineer I Intern - United States
Cisco - Maynard, Massachusetts, US
-
2026 Global Business Development Intern - Falls Church VA
Northrop Grumman - 2 Locations
-
Junior Environmental Scientist
Onterris INC - USA-AR-Little Rock- Northshore Dr
-
Engineer/Scientist - Intern
Onterris INC - USA-NY-Rochester