ASIC Engineer_SoC Design Internship (Armenia)

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified checked Jun 13, 2026

Salary

Not verified

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Entry From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

ASIC Engineer_SoC Design Internship (Armenia) Armenia Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. Meet the Team Cisco is building some of the most complex and advanced silicon in the industry, focusing on high-performance, large-scale SoCs that power next-generation networking platforms. Our team provides an end-to-end view of chip development, offering interns the rare opportunity to work on full-chip and SoC-level designs rather than being limited to a single IP. You will join a collaborative and supportive environment where industry experts with real tape-out experience provide mentorship and structured technical training. The vibe is fast-paced and innovation-driven, perfect for those eager to see how production silicon is built from spec to tape-out. It is an exciting place to gain exposure to the latest silicon technologies and methodologies used in global-scale systems. Your Impact Contribute to the development of state-of-the-art chips by working on full-chip digital design, Design for Test (DFT), and physical design tasks. Develop automation and productivity scripts using Python or Tcl to streamline the ASIC design cycle and improve engineering efficiency. Collaborate with cross-functional teams across design and implementation to ensure seamless integration of complex SoC architectures. Gain hands-on experience with synthesis, floorplanning, and routing to understand the complete RTL-to-GDS flow. This role allows you to make a tangible impact on silicon that powers infrastructure used

Read the full description at cisco.wd5.myworkdayjobs.com. FewerJobs shows a preview and links to the original posting.