ASIC Emulation Engineer / Technical Leader

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified checked Jun 13, 2026

Salary

Not verified

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

Was this benefit information wrong? Tell us.

Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

ASIC Emulation Engineer / Technical Leader Bangalore, India Job Description: Define, design and develop emulation environments needed for complex, large scale networking ASICs. Develop the emulation env, build netlists and use the same to speed up the development cycle and find potential ASIC issues during pre-silicon phase • Work with leading emulation vendors to troubleshoot issues. What You'll Do: Develop state-of-the-art emulation environments that will be used to evaluate the performance and functionality of multi-terabit systems • Developing emulation infrastructure using C/C++ and TCL, Python etc • Developing and testing various emulation flows and contributing to different aspect of ASIC verification for bug free Silicon • Collaborate closely with the design team and the hardware team to verify the ASIC in emulation and during ASIC bring up • Work closely with the design, DV, power, and post-silicon diagnostic teams • Assist with test plan design, test implementation, and debugging during the pre-silicon emulation process • Develop tests to generate complex traffic, performance scenarios to catch potential post Silicon issues during Pre-Silicon phase. Minimum Qualifications: Bachelors + 8 years of related experience, or Masters + 6 years of related experience. Design Emulation background with hands-on experience with emulation platforms like Veloce/Palladium/Zebu as well as experience with compilation, debug, performance testing Fluent in System Verilog or Verilog to work on the Emulation infrastructure development work In-depth knowledge of C/C++, scripting, as well as ASIC design and verification flow Expertise in RTL development for Emulation prototypes System debug experience using tools like gdb,

Read the full description at cisco.wd5.myworkdayjobs.com. FewerJobs shows a preview and links to the original posting.