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ASIC Verification Engineer - 5 to 13 years - Bangalore

Cisco - Bangalore, India

Posted May 12, 2026

Benefits

Parental leave
Not verified
Non-birth-parent leave
Not verified
Family-building benefits
  • Fertility benefits: Not verified
  • Adoption assistance: Not verified
  • Surrogacy assistance: Not verified
Mental health support
Not verified
Relocation assistance
Not verified
Childcare support
Not verified
Learning budget
Not verified
Verification
Not verified checked Jun 13, 2026
Salary
Not verified
401(k) match
Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)
$116,543 U.S. median for this role
Projected growth (BLS Employment Projections)
+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function
Engineering From the posting source checked Jun 20, 2026
Seniority
Mid From the posting source checked Jun 20, 2026

Schedule

Shift type
Not verified
Weekend work
Not verified

Company

Equity
Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter
Not verified
Assessment
Not verified
Deadline
Not stated

Where they hire

State eligibility is not yet verified.

About this role

ASIC Verification Engineer - 5 to 13 years - Bangalore Bangalore, India Define, design and verify ASIC and ASIC subsystems to be deployed in a range of Cisco platforms. Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals for products. Design, document, and develop ASIC subsystems for release in high volume and quality. Help define the process, methods, and tools for design and implementation of complex developments. What You'll Do: • Drives the definition, architecture and design of high performance ASICs • Owns complex or multiple functional areas • Develops reusable code for future projects • Creates re-usable code • Debugs at ASIC, SW, HW level • Works with ASIC and Apps, with limited external scope • Leads design work by solving block level issues and participates in chip level issue resolution • Drives reviews and recognizes areas of architectural concerns • Defines new verification methodologies • Helps in lab bring up • Leads code reviews at platform level • Defines methodologies of execution for analog/mixed signal products • Collaborates with the mixed-signal team and system teams to help define and specify the requirements • Responsible for testing high accuracy analog designs, and helping to suppo • Develops and deploys PD EDA flows • Owns physical design of highly complex blocks • Identifies, designs and implements power and signaling solutions Minimum Qualifications: Typically: Bachelors + 7 years of related experience, or Masters + 4 years of related experience, or PhD + 1 year of related

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Apply link verified; last checked Aug 10, 2026.

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