ASIC Verification Engineer - 5 to 13 years - Bangalore

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified last checked Jun 13, 2026

Salary

Not verified

401(k) match

Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

Was this benefit information wrong? Tell us.

Market context

Role benchmark (BLS OEWS)

$111,944 typical for this role

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

Shift type

Not verified

Weekend work

Not verified

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

ASIC Verification Engineer - 5 to 13 years - Bangalore Bangalore, India Define, design and verify ASIC and ASIC subsystems to be deployed in a range of Cisco platforms. Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals for products. Design, document, and develop ASIC subsystems for release in high volume and quality. Help define the process, methods, and tools for design and implementation of complex developments. What You'll Do: • Drives the definition, architecture and design of high performance ASICs • Owns complex or multiple functional areas • Develops reusable code for future projects • Creates re-usable code • Debugs at ASIC, SW, HW level • Works with ASIC and Apps, with limited external scope • Leads design work by solving block level issues and participates in chip level issue resolution • Drives reviews and recognizes areas of architectural concerns • Defines new verification methodologies • Helps in lab bring up • Leads code reviews at platform level • Defines methodologies of execution for analog/mixed signal products • Collaborates with the mixed-signal team and system teams to help define and specify the requirements • Responsible for testing high accuracy analog designs, and helping to suppo • Develops and deploys PD EDA flows • Owns physical design of highly complex blocks • Identifies, designs and implements power and signaling solutions Minimum Qualifications: Typically: Bachelors + 7 years of related experience, or Masters + 4 years of related experience, or PhD + 1 year of related

Read the full description at cisco.wd5.myworkdayjobs.com. FewerJobs shows a source-linked preview and links to the original posting.