ASIC Design Verification Engineer I Intern - United States

Verified benefits

Parental leave

13 weeks

Non-birth-parent leave

13 weeks

Verified

Yes last checked unknown

Salary

$44K-$185K

401(k) match

Listed

Market context

Median wage (BLS OEWS)

$116,543 national median

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

About in line with the BLS national median for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Where they hire

State eligibility is not yet verified.

About this role

ASIC Design Verification Engineer I Intern - United States Maynard, Massachusetts, US Please note this posting is to advertise potential job opportunities. This exact role may not be open today

Read the full description at cisco.wd5.myworkdayjobs.com. FewerJobs shows a source-linked preview and links to the original posting.