ASIC Design Verification Engineer | 7+ Yrs | BLR

Verified benefits

Parental leave

13 weeks

Non-birth-parent leave

13 weeks

Verified

Yes last checked unknown

Salary

Not disclosed

Market context

Median wage (BLS OEWS)

$66,396 national median

Projected growth (BLS Employment Projections)

+3.5% - Average

Matched to SOC 27-1024 - Design aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Where they hire

State eligibility is not yet verified.

About this role

ASIC Design Verification Engineer | 7+ Yrs | BLR Bangalore, India Meet the Team: The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching,

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