Mgr Product Engineering
Rambus INC - Taipei, UNAVAILABLE, JP; Taipei, UNAVAILABLE, JP
Posted Jan 23, 2026
Benefits
- Parental leave
- Not verified
- Non-birth-parent leave
- Not verified
- Family-building benefits
-
- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
- Not verified
- Relocation assistance
- Not verified
- Childcare support
- Not verified
- Learning budget
- Not verified
- Verification
- Not verified last checked Jun 13, 2026
- Salary
- Not verified
- 401(k) match
- Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.
Was this benefit information wrong? Tell us.
Market context
- U.S. role benchmark (BLS OEWS)
- $111,944 U.S. median for this role
- Projected growth (BLS Employment Projections)
- +13.7% - Much faster than average
Matched to SOC 15-1252 - Data and ML aggregate by role bucket.
Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.
Schedule
- Shift type
- Not verified
- Weekend work
- Not verified
Application
- Cover letter
- Not verified
- Assessment
- Not verified
- Deadline
- Not stated
Where they hire
State eligibility is not yet verified.
About this role
Mgr Product Engineering Taipei, UNAVAILABLE, JP; Taipei, UNAVAILABLE, JP Overview Mgr Product Engineering (based in Korea or Taiwan) will join a dynamic and multi-disciplinary team which will ensure product reliability and gross margins meet expectations for products in our memory and interface division. This engineer will be responsible for day-to-day product engineering activities by collaborating within a cross-functional team including test engineers, OSATs and fabs. Candidates for this level position must be capable of working independently, defining technical direction, be self-motivated and a collaborative team player Responsibilities Bring-up and debug first silicon quickly to identify any potential design, process or testing issues. · Ramp up yield for new product introduction. · Perform yield analysis to ensure products yield to D0 projections. · Identify the low yield detractors and the root cause. · Work with Taiwan/Korean subcontractors to ensure smooth production, for both Wafer Sort and Final Test, on the day-to-day basis: tester correlation, hold lot disposition etc. · Generate real time SBL and SYL for all products to identify production outliers. · Generate customer reports per commitment. · Identify areas of improvement in current productions. · Drive test time reduction to product COG metric or below. · Help to manage WIP & cycle time and provide constructive feedback to improve. Qualifications BSEE required, MSEE preferred. · 15+ of experience with product/test engineering. · Programming skills preferred (C++, Java script or Python experience). · Wafer Sorting (WS) and FT NPI setup/production experience preferred. · Strong test data analysis capability. (Synopsis, Galaxy,
Read the full description at careers-rambus.icims.com. FewerJobs shows a source-linked preview and links to the original posting.
Apply link verified; last checked Jun 13, 2026.
What verified means
Verified means a displayed claim has a recorded source field, a source URL when available, and a timestamp showing when FewerJobs checked or enriched the evidence.
Related jobs
-
ASIC Package Engineer
Cisco - Taipei, Taiwan
-
Technical Leader Component & Laser Reliability Engineer
Cisco - Taipei, Taiwan
-
Memory CAD Engineer
Cisco - Zhubei, Taiwan
-
Component Engineer
Cisco - Taipei, Taiwan