Senior ASIC-FPGA Verification Engineer

Verified benefits

Parental leave

12 weeks source

Non-birth-parent leave

12 weeks

Verified

Yes last checked 2026-05-07

Salary

Not disclosed

Market context

Median wage (BLS OEWS)

$116,543 national median

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Where they hire

State eligibility is not yet verified.

About this role

Senior ASIC-FPGA Verification Engineer IND - Bangalore, India Senior ASIC-FPGA Verification Engineer /job/IND---Bangalore-India/Lead-ASIC-FPGA-Verification-Engineer_JR2026501458-1 IND - Bangalore, India Posted 9 Days Ago Hybrid Job

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