Senior Verification Engineer

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified

Salary

Not verified

Was this benefit information wrong? Tell us.

Schedule

Shift type

Not verified

Weekend work

Not verified

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Senior Verification Engineer Hyderabad, Telangana, India AST SpaceMobile is building the first and only global cellular broadband network in space to operate directly with standard, unmodified mobile devices based on our extensive IP and patent portfolio and designed for both commercial and government applications. Our engineers and space scientists are on a mission to eliminate the connectivity gaps faced by today's five billion mobile subscribers and finally bring broadband to the billions who remain unconnected. Position Overview We are seeking a Senior FPGA Verification Engineer with 4-8 years of experience to design, develop, and execute comprehensive verification strategies for complex FPGA designs. This role requires strong hands-on expertise in SystemVerilog and UVM, testbench architecture, and cross-functional collaboration with design and system teams. Key Responsibilities: - Develop and maintain SystemVerilog/UVM-based verification environments for FPGA block-level and top-level designs - Create and execute verification plans , directed and constrained-random test scenarios, assertions, and functional coverage - Perform simulation-based verification of FPGA designs using industry-standard simulators - Drive debug and root-cause analysis of functional issues and work closely with FPGA RTL designers - Integrate and maintain VIPs, scoreboards, checkers, and reference models - Support FPGA bring-up , validation, and debug activities on FPGA platforms and evaluation boards - Review FPGA RTL, verification code, and test plans to ensure quality and completeness - Mentor junior engineers and contribute to FPGA verification best practices - Support regression runs, coverage closure, and release signoff Qualifications Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or

Read the full description at ast-science.com. FewerJobs shows a source-linked preview and links to the original posting.