Senior Verification Engineer

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Senior From the posting source checked Jun 20, 2026

Schedule

Shift type

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Weekend work

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Company

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

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Assessment

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Deadline

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Where they hire

State eligibility is not yet verified.

About this role

Senior Verification Engineer Hyderabad, Telangana, India AST SpaceMobile is building the first and only global cellular broadband network in space to operate directly with standard, unmodified mobile devices based on our extensive IP and patent portfolio and designed for both commercial and government applications. Our engineers and space scientists are on a mission to eliminate the connectivity gaps faced by today's five billion mobile subscribers and finally bring broadband to the billions who remain unconnected. Position Overview We are seeking a Senior FPGA Verification Engineer with 4-8 years of experience to design, develop, and execute comprehensive verification strategies for complex FPGA designs. This role requires strong hands-on expertise in SystemVerilog and UVM, testbench architecture, and cross-functional collaboration with design and system teams. Key Responsibilities: - Develop and maintain SystemVerilog/UVM-based verification environments for FPGA block-level and top-level designs - Create and execute verification plans , directed and constrained-random test scenarios, assertions, and functional coverage - Perform simulation-based verification of FPGA designs using industry-standard simulators - Drive debug and root-cause analysis of functional issues and work closely with FPGA RTL designers - Integrate and maintain VIPs, scoreboards, checkers, and reference models - Support FPGA bring-up , validation, and debug activities on FPGA platforms and evaluation boards - Review FPGA RTL, verification code, and test plans to ensure quality and completeness - Mentor junior engineers and contribute to FPGA verification best practices - Support regression runs, coverage closure, and release signoff Qualifications Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or

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