SoC Integration and Synthesis Engineer
Apple - Cupertino, United States of America
Posted Oct 30, 2025
Benefits
- Parental leave
- Not verified
- Non-birth-parent leave
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- Family-building benefits
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- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
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- Relocation assistance
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- Childcare support
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- Learning budget
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- Verification
- Not verified last checked Jun 13, 2026
- Salary
- Not verified not verified - source not recorded; timestamp not recorded
- 401(k) match
- Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.
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Schedule
- Shift type
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- Weekend work
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Application
- Cover letter
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- Assessment
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- Deadline
- Not stated
Where they hire
State eligibility is not yet verified.
About this role
SoC Integration and Synthesis Engineer Cupertino, United States of America Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will be part of a group that defines flows and methodologies in all these fields that help Apple implement complex chips with the best QOR (quality of results) and PPA (power, performance, and area) using cutting-edge technologies. We are searching for a talented engineer to join our exciting team of problem solvers. As an SOC/ASIC Integration & Synthesis Engineer, you will have responsibilities spanning various aspects of SOC design: - Drive all front-end integration activities like Integration, Synthesis, UPF, Logical Equivalence, ECO, etc. - Work closely on methodology improvements for improving synthesis QOR. - Work on Low power design, writing UPFs, close on power intent verification at the chip level. - Work on RTL integration, timing constraints, and synthesis of designs. - Knowledge of FE flows like Lint & LEQ and scripting is a plus Work closely with other engineers that are members of the SOC Design, SOC Design Verification, Emulation, STA, Power, and Physical Design teams. Minimum Qualifications: BS degree
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