SerDes Micro Architect

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified checked Jun 13, 2026

Salary

$181K-$318K From the posting source checked Jun 20, 2026

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

114% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Staff Plus From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

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Company

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

SerDes Micro Architect Cupertino, United States of America Analog Mixed-Signal (AMS) Team is seeking a self-motivated SERDES Micro Architect to drive the definition of our next generation IPs. The SERDES IPs will be used in Apple silicon offering breakthrough power and performance for iPhone, iPad, Mac, and Apple Watch. You will define the Micro Architecture of analog mixed-signal IPs with emphasis on SERDES design. You will review firmware code, analog and digital circuits and will verify that the design meets performance requirements. You will work with silicon evaluation and design verification teams to define expected behavior. You would lead the debug effort in system bring up and factory test. You will work with signal integrity engineers to determine system requirements. Minimum Qualifications: BS degree in technical discipline with minimum 10 years of relevant experience. Preferred Qualifications: Experience leading the definition of high-speed SERDES receiver, transmitter, and clocking blocks Deep understanding of adaptation and optimization algorithms Deep understanding of communications and information theory Proficiency in equalizers, timing recovery and system identification Proficiency in DSP concepts and applications Familiarity with mixed-signal modeling in Python/MATLAB/C/C++ Experience in system design and performance tradeoff Familiarity with simulation tools for analog, digital, and/ or mixed-signal circuits Familiarity with Machine Learning concepts Experience in firmware or embedded software development is a plus

Read the full description at jobs.apple.com. FewerJobs shows a preview and links to the original posting.