Power & Performance Engineer - Platform Architecture

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified last checked Jun 13, 2026

Salary

Not verified not verified - source not recorded; timestamp not recorded

401(k) match

Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

Was this benefit information wrong? Tell us.

Schedule

Shift type

Not verified

Weekend work

Not verified

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Power & Performance Engineer - Platform Architecture Santa Clara, United States of America Are you highly detailed and skilled at developing creative solutions? Are you obsessed with understanding how things work, function and fit together at the component and system level? Do you love focusing on the smallest details and applying this knowledge to much larger product level decisions to inform roadmap? In this role you will work with a team to understand highly complex systems and their impact on Power, Performance, and SoC design/integration to inform future direction. This work is a vital component of the quality and efficiency of Apple's future products. Join this group, and you'll have a direct impact on the technology that shapes Apple's customer experiences. Together, our work will be the reason millions of customers feel they can trust their devices every single day and directly impact the success of future products. Apple's Platform Architecture group is looking for a motivated, curiosity driven Engineer looking to deprocess, image, and analyze silicon to extract critical intelligence on process technology, circuit design choices, memory architectures, and logic implementation efficiency - directly informing Apple's silicon roadmap and design. Minimum Qualifications: BS in EE, Materials Science, Physics, similar engineering degree or equivalent work experience. Experience in semiconductor physical analysis including layer-by-layer deprocessing (chemical etch, mechanical polish, pFIB), SEM/TEM/FIB imaging, or EDS characterization of SoCs. Preferred Qualifications: MS, or PhD in EE, Materials Science, Physics, or similar engineering degree. . 10 years industry experience. Familiarity with silicon implementation and

Read the full description at jobs.apple.com. FewerJobs shows a source-linked preview and links to the original posting.