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ASIC Design Engineer - Cache Controller

Apple - Santa Clara, United States of America

Posted Apr 10, 2026

Benefits

Parental leave
Not verified
Non-birth-parent leave
Not verified
Family-building benefits
  • Fertility benefits: Not verified
  • Adoption assistance: Not verified
  • Surrogacy assistance: Not verified
Mental health support
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Relocation assistance
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Childcare support
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Learning budget
Not verified
Verification
Not verified checked Jun 13, 2026
Salary
$147K-$272K From the posting source checked Jun 20, 2026
401(k) match
Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)
$116,543 U.S. median for this role
Projected growth (BLS Employment Projections)
+9.8% - Much faster than average

80% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function
Engineering From the posting source checked Jun 20, 2026
Seniority
Mid From the posting source checked Jun 20, 2026

Schedule

Shift type
Not verified
Weekend work
Not verified

Company

Company stage
Public-company From the posting source checked Jun 20, 2026
Equity
Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter
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Assessment
Not verified
Deadline
Not stated

Where they hire

State eligibility is not yet verified.

About this role

ASIC Design Engineer - Cache Controller Santa Clara, United States of America Apple is building the world's fastest highly parallel mobile processing systems. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. As we increase levels of parallelism, bandwidth and capacity, we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency, and high-bandwidth. In this role, you will work on crafting special purpose cache and controller which is part and parcel of the SOC memory hierarchy. Design and develop hardware for cache subsystem in high performance system on a chip (SoC). Develop cache micro-architecture based on architecture guidelines and model analysis. Explore architecture trade-offs in system performance, area, and power consumption. Develop and debug register-transfer level (RTL) design of various sections in the cache subsystem. Work on front-end netlist and area/timing analysis of the cache subsystem. Work with physical design team on the timing closure of the cache subsystem. Minimum Qualifications: 3+ years of full time ASIC design experience memory system development RTL/micro-architecture definition PPA (performance/power/area) analysis B.S. in a relevant field Preferred Qualifications: Cache design background including good understanding of different memory organizations and tradeoffs Experience with multi-processor cache coherence protocols Knowledge of high-performance coherent memory systems or interconnect architectures Knowledge of high-performance DRAM controller M.S in a relevant field.

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