Analog IC Design Engineer
Apple - Cupertino, United States of America
Posted Jun 10, 2026
Benefits
- Parental leave
- Not verified
- Non-birth-parent leave
- Not verified
- Family-building benefits
-
- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
- Not verified
- Relocation assistance
- Not verified
- Childcare support
- Not verified
- Learning budget
- Not verified
- Verification
- Not verified checked Jun 13, 2026
- Salary
- $181K-$318K From the posting source checked Jun 20, 2026
- 401(k) match
- Reported from DOL Form 5500 industry filing (not employer-specific)
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Market context
- U.S. role benchmark (BLS OEWS)
- $116,543 U.S. median for this role
- Projected growth (BLS Employment Projections)
- +9.8% - Much faster than average
114% above the BLS role benchmark for software engineering aggregate.
Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.
Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.
Role
Schedule
- Shift type
- Not verified
- Weekend work
- Not verified
Company
Application
- Cover letter
- Not verified
- Assessment
- Not verified
- Deadline
- Not stated
Where they hire
State eligibility is not yet verified.
About this role
Analog IC Design Engineer Cupertino, United States of America At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a visionary and uncommonly talented IC Designer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple's customers every single day. In this role, the key responsibilities are the following: Involved in specifications of analog portions of IC. Behavioral modeling to validate architectures. Transistor-level feasibility studies for various blocks in ADC/DAC. Crafting blocks and documenting design towards formal design reviews. Drive mask design to implement layout view of designs. Top-level simulations to validate top-level integration. Defining production/bench-level test-plans. Taking lab measurements to validate analog designs. Driving/reviewing yield/lab test results to drive bug fixes. Design for ESD compliance. Minimum Qualifications: Bachelor's of Science in Electric Engineering with 10+ years of relevant experience preferred Preferred Qualifications: Do you have a proven track record of taking chips to production in the following areas? Deep knowledge of ADC/DAC architectures and knowing which are suitable for given applications Deep knowledge of band-gaps, bias, op-amps, switched-cap circuits, LDOs, feedback and compensation techniques Proven expertise in the following areas: Significant knowledge of low noise design techniques Significant knowledge of high precision techniques in presence of device mismatch Experience in C / Matlab / Verilog
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