AMS SerDes Robustness Analysis Validation Architect

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified last checked Jun 13, 2026

Salary

Not verified not verified - source not recorded; timestamp not recorded

401(k) match

Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

Was this benefit information wrong? Tell us.

Schedule

Shift type

Not verified

Weekend work

Not verified

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

AMS SerDes Robustness Analysis Validation Architect San Francisco Bay Area, United States of America Are you inherently curious, hands-on, and analytical? We are seeking a seasoned SerDes Robustness Analysis & Validation Architect with a strong technical foundation and a hands-on approach to drive the robustness, performance, and margin validation of high-speed SerDes PHYs, such PCIe and USB, within our system. This role is ideal for someone who is motivated to push designs to the edge through intentional stress testing and margin-finding techniques! You will architect validation strategies that go beyond traditional spec-checking, focusing on uncovering weaknesses in design assumptions, stress-to-fail conditions, and system interactions across wide-ranging PVT and real-world scenarios, including edge case behaviors. A deep understanding of SerDes design and validation principles, SOC/system integration, and real-world system environments is required. The role demands strong collaboration with design, architecture, and system teams to ensure the IP is designed with design for testability. In addition, you will also partner closely with the validation team to help optimize for maximum test coverage vs. execution time, ensuring efficient yet thorough validation. This is a hands-on lab role that requires close collaboration with designers, architects, system, and test engineers to validate next-generation SerDes IPs from design conception through production. Define and architect margin-to-fail validation strategies to uncover weaknesses and failure conditions in high-speed SerDes PHYs across multiple process, voltage, temperature, and different system environments. Develop and implement stress-to-fail methodologies, covering end-to-end systems, such as stressing equalization paths, clocking structures, jitter sensitivities, and link training

Read the full description at jobs.apple.com. FewerJobs shows a source-linked preview and links to the original posting.