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Senior/Principal Analog Layout Engineer

Ametek - Work Location (Country) India | Remote/Onsite Onsite

Posted Jun 12, 2026

Benefits

Parental leave
Not verified
Non-birth-parent leave
Not verified
Family-building benefits
  • Fertility benefits: Not verified
  • Adoption assistance: Not verified
  • Surrogacy assistance: Not verified
Mental health support
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Relocation assistance
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Childcare support
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Learning budget
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Verification
Not verified checked Jun 13, 2026
Salary
Not verified
401(k) match
Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)
$55,390 U.S. median for this role
Projected growth (BLS Employment Projections)
-0.1% - Decline

Matched to SOC 25-2021 - Teaching and Education aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function
Teaching Education From the posting source checked Jun 20, 2026
Seniority
Principal From the posting source checked Jun 20, 2026
Work mode
Remote From the posting source checked Jun 20, 2026
In-office days
0 days From the posting source checked Jun 20, 2026

Schedule

Shift type
Not verified
Weekend work
Not verified

Company

Company stage
Public-company From the posting source checked Jun 20, 2026
Equity
Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter
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Assessment
Not verified
Deadline
Not stated

Where they hire

State eligibility is not yet verified.

About this role

Senior/Principal Analog Layout Engineer Work Location (Country) India | Remote/Onsite Onsite The Senior Analog Layout Engineer will be responsible for creating high‑performance IC layouts for complex analog, mixed‑signal, and custom circuits at both block and chip levels. This role requires a strong understanding of deep‑submicron CMOS processes, advanced layout techniques, and industry‑standard EDA tools. The ideal candidate will work closely with circuit designers to translate schematic requirements into robust, silicon‑proven physical layouts. Primary Responsibilities: Perform full‑custom layout of analog and mixed‑signal building blocks, including amplifiers, ADC/DAC components, regulators, PLLs, bias circuits, sensors, and high‑precision analog modules. Execute top‑level floorplanning and routing strategies with careful consideration of performance, area optimization, power distribution, and signal integrity. Apply advanced matching techniques for transistors, resistors, and capacitors, ensuring low noise, high linearity, and optimal device performance in deep‑submicron technologies. Verify and debug physical layouts by resolving LVS, DRC, ERC, Antenna, and EM/IR reliability issues. Collaborate closely with circuit designers to understand layout‑dependent effects (LDE), performance trade‑offs, and design constraints. Ensure compliance with foundry technology rules and design guidelines while optimizing for manufacturability and yield (DFM). Generate and maintain documentation related to layout methodologies, constraints, and verification results. Position Requir

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