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ASIC Engineering Layout Leader | Custom IC layout, Analog, Mixed-signal, and high-speed designs | 12+ years, Bangalore

Cisco - Bangalore, India

Posted Jun 11, 2026

Benefits

Parental leave
Not verified
Non-birth-parent leave
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Family-building benefits
  • Fertility benefits: Not verified
  • Adoption assistance: Not verified
  • Surrogacy assistance: Not verified
Mental health support
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Relocation assistance
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Childcare support
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Learning budget
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Verification
Not verified checked Jun 13, 2026
Salary
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401(k) match
Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)
$116,543 U.S. median for this role
Projected growth (BLS Employment Projections)
+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function
Engineering From the posting source checked Jun 20, 2026
Seniority
Mid From the posting source checked Jun 20, 2026

Schedule

Shift type
Not verified
Weekend work
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Company

Company stage
Public-company From the posting source checked Jun 20, 2026
Equity
Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter
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Assessment
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Deadline
Not stated

Where they hire

State eligibility is not yet verified.

About this role

ASIC Engineering Layout Leader | Custom IC layout, Analog, Mixed-signal, and high-speed designs | 12+ years, Bangalore Bangalore, India Meet the Team At Cisco Systems , the Client Optics Group (COG) Engineering team is at the forefront of building next-generation optical interconnect solutions powering high-speed networking. The team focuses on delivering cutting-edge 100G, 200G, and 400G per lambda technologies that enable scalable, high-performance data movement across modern infrastructure. As a Layout Lead, you will work within a highly collaborative, cross-functional environment alongside analog and mixed-signal designers, digital engineers, packaging experts, process technologists, and validation teams. Together, you will drive end-to-end development of complex silicon solutions that are critical to Cisco's innovation in optics and high-speed connectivity. Your Impact In this role, you will provide technical leadership and drive the physical implementation of high-performance analog and mixed-signal designs from concept through tapeout. You will: Lead end-to-end layout development for complex analog, mixed-signal, and high-speed circuits including SerDes and PAM4 interfaces Own block-level and top-level floorplanning, placement, routing, and integration Translate circuit schematics and performance requirements into optimized, manufacturable layouts Optimize designs for parasitics, matching, signal integrity, power integrity, thermal behavior, and yield Ensure compliance with all physical verification requirements (DRC, LVS, ERC, EM/IR, density, reliability) Drive integration across analog, digital, and high-speed domains including clocking and control logic Support post-layout extraction, simulation closure, and tapeout readiness Partner with packaging teams on bump planning, pad ring, ESD, and overall package integration Identify and resolve layout challenges impacting performance, yield, or manufacturability Lead

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Apply link verified; last checked Aug 10, 2026.

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