Senior ASIC Design Engineer, Amazon Leo
Amazon - San Diego, California, USA
Posted Apr 7, 2026
Benefits
- Parental leave
- 6 weeks From the posting source checked Jun 20, 2026
- Non-birth-parent leave
- 6 weeks From the posting source checked Jun 20, 2026
- Family-building benefits
- Mental health support
- Offered From the posting source checked Jun 20, 2026
- Relocation assistance
- Not verified
- Childcare support
- Offered From the posting source checked Jun 20, 2026
- Learning budget
- Not verified
- Verification
- Source-linked checked Jun 7, 2026
- Salary
- $159K-$215K From the posting source checked Jun 20, 2026
- 401(k) match
- Reported from DOL Form 5500 industry filing (not employer-specific)
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Market context
- U.S. role benchmark (BLS OEWS)
- $116,543 U.S. median for this role
- Projected growth (BLS Employment Projections)
- +9.8% - Much faster than average
61% above the BLS role benchmark for software engineering aggregate.
Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.
Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.
Role
Schedule
- Shift type
- Not verified
- Weekend work
- Not verified
Company
Application
- Cover letter
- Not verified
- Assessment
- Not verified
- Deadline
- Not stated
Where they hire
State eligibility is not yet verified.
About this role
Senior ASIC Design Engineer, Amazon Leo San Diego, California, USA Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. The Role: Be part of Amazon Leo's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution with few legacy constraints. The team works with customer requirements and wireless system teams to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies. In this role you will: · Implement wireless system architecture in silicon from system specification to chip specification to RTL to optimizing timing / power to chip level validation · Develop solutions optimizing customer experience (throughput, latency, and availability) while meeting power and cost constraints · Drive high quality designs for first-time right silicon solutions, and meeting the power objectives · Create standalone verification test bench to verify the correctness of your block · Work with the verification team and participate in System level verification using test benches constructed using UVM, System C and DPI-C · Ensure that the block meets DFT, timing and power targets by working closely with the implementation team · Learn about requirements and solutions for systems operating in space · Drive trade-off analysis to benefit customer experience and optimization of resources (costs, power, spectrum) Export Control Requirement: Due to
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