Lead ASIC Modem Design Engineer, Amazon Leo

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

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Salary

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401(k) match

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Market context

Median wage (BLS OEWS)

$111,944 national median

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

67% above the BLS national median for data and ml aggregate.

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

Shift type

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Weekend work

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Application

Cover letter

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Assessment

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Deadline

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Where they hire

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About this role

Lead ASIC Modem Design Engineer, Amazon Leo San Diego, California, USA Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. Come work at Amazon! We're hiring a Lead Modem Engineer within a high performance ASIC design team. This team is using industry leading methodologies to develop proprietary IP's. The Role: Be part of Leo's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution with few legacy constraints. The team works with customer requirements and wireless system teams to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies. In this role you will: · Implement wireless system architecture in silicon from system specification to chip specification to RTL to optimizing timing / power to chip level validation. · Develop solutions optimizing customer experience (throughput, latency, and availability) while meeting power and cost constraints. · Drive high quality designs for first-time right silicon solutions, and meeting the power objectives · Create standalone verification test bench to verify the correctness of your block. · Work with the verification team and participate in System level verification using test benches constructed using UVM, System C and DPI-C. · Ensure that the block meets DFT, timing and power targets by working closely with the implementation team. · Learn about

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