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Silicon Design-for-Test (DFT) Engineer Mountain View, CA What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking a Silicon Design-For-Test (DFT) engineer to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The successful candidate for this role will be responsible for implementation of DFT functions for performant and functionally accurate silicon for MatX products across compute, memory management, high-speed connectivity and other key technologies in leading-edge process nodes. What You'll Do Here - Design and develop functional test solutions for SERDES PHY , covering loopback, eye diagram characterization, and margin testing. - Perform DFT integration of PHY IP blocks, including boundary scan, BIST interfaces, and test mode control signals, and develop robust pattern porting flows from IP-level to SoC-level. - Develop and maintain firmware loading flows for PHY bring-up and test - including SPI/JTAG-based firmware download, register initialization sequences, and debug support during test program development. - Collaborate closely with verification, firmware, and test engineering teams to develop and bring up silicon test programs from simulation to ATE. - Execute DFT implementation and verification flows for block-level DFT insertion , including scan chain closure, ATPG pattern generation, and sign-off. - Support test escapes root cause analysis and drive continuous improvement of DFT coverage and test quality. Who You Are - Hands-on

DFX Engineer Sunnyvale, CA Meta is at the forefront of developing innovative hardware that redefines how people experience the world - from virtual and augmented reality technology. The DFX team is a critical pillar of this mission, ensuring that our advanced devices are not only advanced in function but also manufacturable at scale with the highest standards of quality, cost-efficiency, and reliability. As a DFX Engineer, you will be a vital member of this team, directly influencing the quality, cost, and delivery of advanced Meta devices by creating and implementing solutions for complex manufacturing challenges. Your work will span the entire product lifecycle - from initial concept through to mass production - making this a uniquely impactful engineering role. Responsibilities: - This position sits within the NPI & Manufacturing Engineering team and demands close partnership with Hardware Engineering, Quality, Test Engineering, and our external manufacturing partners. You will be responsible for defining and enforcing manufacturing process best practices as they relate to product design, serving as the critical bridge between design intent and production reality - On a day-to-day basis, you will partner with cross-functional Engineering teams to identify and resolve manufacturing challenges by applying DFX principles and establishing robust Design for Manufacturing (DFM) guidelines. You will develop manufacturing assembly processes, fixtures, and equipment requirements, and will drive line and fixture qualifications to meet Meta's rigorous standards - A core part of your mandate will be to engineer new or improved manufacturing processes through the application of both theoretical and

Reliability/DFX Engineer San Francisco, California, United States About the Team OpenAI's Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI's supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI. About the Role We are seeking a highly skilled cross-stack engineer with deep expertise in making ML systems reliable at scale. This hands-on individual contributor will sit within our hardware team and work closely with chip design, platform design, hardware health, and the broader industry ecosystem to architect, implement, and deploy reliable next-generation AI accelerator systems. This engineer will evaluate system and chip architecture holistically, identify high-ROI opportunities to improve reliability and availability across the stack, and translate those opportunities into strategy and silicon features. In this role, you will: - Oversee DFX architecture, implementation, and execution in silicon from concept to high-volume deployment, and propose high-ROI features to enhance reliability and fault tolerance. DFX includes design for testability, reliability, availability, and serviceability of high-performance AI hardware. - Build system-level reliability models grounded in empirical data to guide organization-wide DFX and reliability strategy. This requires a detailed understanding of chip and system architecture, design, implementation, and component-level reliability. - Collaborate with chip and platform architecture/design teams

ASIC DFT CAD Technical Leader San Jose, California, US The application window is expected to close on: 07/24/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Who We Are: The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's revolutionary solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Key Responsibilities: Own and drive end-to-end DFT flow architecture. Build and maintain scalable DFT CAD infrastructure from RTL ‚ DFT insertion, ATPG, simulation, reporting. Develop robust regression frameworks (LSF/cluster-based) with job orchestration, monitoring, logging, and failure recovery. Lead AI-driven automation initiatives for log analysis, failure triage, regression optimization, and intelligent debug. Collaborate with RTL, Physical Design, and Validation teams to ensure seamless DFT integration and signoff. Define and track key metrics (coverage, pattern count, runtime, regression health) and build dashboards for visibility. Standardize flows, improve reusability, and