ASIC DFT CAD Technical Leader

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

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Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified last checked Jun 13, 2026

Salary

$184K-$264K not verified - source not recorded; timestamp not recorded

401(k) match

Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

92% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

Shift type

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Weekend work

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Application

Cover letter

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Assessment

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Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

ASIC DFT CAD Technical Leader San Jose, California, US The application window is expected to close on: 07/24/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Who We Are: The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's revolutionary solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Key Responsibilities: Own and drive end-to-end DFT flow architecture. Build and maintain scalable DFT CAD infrastructure from RTL ‚ DFT insertion, ATPG, simulation, reporting. Develop robust regression frameworks (LSF/cluster-based) with job orchestration, monitoring, logging, and failure recovery. Lead AI-driven automation initiatives for log analysis, failure triage, regression optimization, and intelligent debug. Collaborate with RTL, Physical Design, and Validation teams to ensure seamless DFT integration and signoff. Define and track key metrics (coverage, pattern count, runtime, regression health) and build dashboards for visibility. Standardize flows, improve reusability, and

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