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Associate Director – AI Software, Applied Research & Technology – Defense Technologies (Onsite)
Raytheon Technologies - US-IA-CEDAR RAPIDS-108 ~ 400 Collins Rd NE ~ BLDG 108Indexed from Workday Benefit evidence checked May 7, 2026posted 187 days agoWhy we showed this
Description: "technologies"Employer: "technologies"+3
Onsite - 5d office From the posting source Data From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedAssociate Director – AI Software, Applied Research & Technology – Defense Technologies (Onsite) US-IA-CEDAR RAPIDS-108 ~ 400 Collins Rd NE ~ BLDG 108 posted: Posted 30+ Days Ago
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Mechanical Assembler II (Onsite)
Raytheon Technologies - US-TX-SAN MARCOS-2005 ~ 2005 Technology Wy ~ TECHNOLOGYIndexed from Workday Benefit evidence checked May 7, 2026posted 172 days agoWhy we showed this
Employer: "technologies"Employer: semantic match+1
Onsite - 5d office From the posting source Trades From the posting source - Mid From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedMechanical Assembler II (Onsite) US-TX-SAN MARCOS-2005 ~ 2005 Technology Wy ~ TECHNOLOGY posted: Posted 16 Days Ago
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Welder II (Onsite)
Raytheon Technologies - US-TX-SAN MARCOS-2005 ~ 2005 Technology Wy ~ TECHNOLOGYIndexed from Workday Benefit evidence checked May 7, 2026posted 172 days agoWhy we showed this
Employer: "technologies"Employer: semantic match+1
Onsite - 5d office From the posting source Trades From the posting source - Mid From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedWelder II (Onsite) US-TX-SAN MARCOS-2005 ~ 2005 Technology Wy ~ TECHNOLOGY posted: Posted 16 Days Ago
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Senior Systems Engineer - Onsite Cambridge MA
Raytheon Technologies - US-MA-CAMBRIDGE-555-CUST ~ 555 Technology Sq ~ TECHNOLOGY (External Site)Indexed from Workday Benefit evidence checked May 7, 2026posted 160 days agoWhy we showed this
Employer: "technologies"Employer: semantic match+1
Onsite - 5d office From the posting source Engineering From the posting source - Senior From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSenior Systems Engineer - Onsite Cambridge MA US-MA-CAMBRIDGE-555-CUST ~ 555 Technology Sq ~ TECHNOLOGY (External Site) posted: Posted 4 Days Ago
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Leader qualité et des technologies de données | Quality Operation Lead and Data Technologies
Raytheon Technologies - CA-QC-LONGUEUIL-J01 ~ 1000 Blvd Marie-Victorin ~ J01 BLDGIndexed from Workday Benefit evidence checked May 7, 2026posted 156 days agoWhy we showed this
Description: "technologies"Employer: "technologies"+3
Unspecified Data From the posting source - Senior From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedLeader qualité et des technologies de données | Quality Operation Lead and Data Technologies CA-QC-LONGUEUIL-J01 ~ 1000 Blvd Marie-Victorin ~ J01 BLDG posted: Posted Today
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Assembler II (1st Shift)
Raytheon Technologies - US-TX-SAN MARCOS-2005 ~ 2005 Technology Wy ~ TECHNOLOGYIndexed from Workday Benefit evidence checked May 7, 2026posted 170 days agoWhy we showed this
Employer: "technologies"Employer: semantic match+1
Unspecified Trades From the posting source - Mid From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedAssembler II (1st Shift) US-TX-SAN MARCOS-2005 ~ 2005 Technology Wy ~ TECHNOLOGY posted: Posted 14 Days Ago
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Technology & Digital
Kroger - Location not specifiedIndexed from Oraclecloud Benefit evidence checked May 7, 2026posted 164 days agoWhy we showed this
Title: semantic matchSource-backed benefits+1
Unspecified Marketing From the posting source - Mid From the posting source Resolvable source Verified parental leave: 2 wksource Resolvable source Verified non-birth-parent leave: 2 wksource Salary not disclosed EquityTechnology & Digital Technology & Digital
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Assembler II (2nd Shift)
Raytheon Technologies - US-TX-SAN MARCOS-2005 ~ 2005 Technology Wy ~ TECHNOLOGYIndexed from Workday Benefit evidence checked May 7, 2026posted 170 days agoWhy we showed this
Employer: "technologies"Employer: semantic match+1
Unspecified Trades From the posting source - Mid From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedAssembler II (2nd Shift) US-TX-SAN MARCOS-2005 ~ 2005 Technology Wy ~ TECHNOLOGY posted: Posted 14 Days Ago
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Assembler II (3rd Shift)
Raytheon Technologies - US-TX-SAN MARCOS-2005 ~ 2005 Technology Wy ~ TECHNOLOGYIndexed from Workday Benefit evidence checked May 7, 2026posted 170 days agoWhy we showed this
Employer: "technologies"Employer: semantic match+1
Unspecified Trades From the posting source - Mid From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedAssembler II (3rd Shift) US-TX-SAN MARCOS-2005 ~ 2005 Technology Wy ~ TECHNOLOGY posted: Posted 14 Days Ago
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Principal Systems Engineer Onsite - Cambridge MA
Raytheon Technologies - US-MA-CAMBRIDGE-555-CUST ~ 555 Technology Sq ~ TECHNOLOGY (External Site)Indexed from Workday Benefit evidence checked May 7, 2026posted 157 days agoWhy we showed this
Employer: "technologies"Employer: semantic match+1
Onsite - 5d office From the posting source Engineering From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedPrincipal Systems Engineer Onsite - Cambridge MA US-MA-CAMBRIDGE-555-CUST ~ 555 Technology Sq ~ TECHNOLOGY (External Site) posted: Posted Yesterday
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Technology Director - Integrated Manufacturing Technologies - Aerospace Research
GE Aerospace - NiskayunaIndexed from Workday Benefit evidence checked Jun 7, 2026posted 187 days agoWhy we showed this
Description: "technologies"Title: "technologies"+2
Unspecified Data From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 10 wksource Resolvable source Verified non-birth-parent leave: 10 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedTechnology Director - Integrated Manufacturing Technologies - Aerospace Research Niskayuna posted: Posted 30+ Days Ago
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Digital Technology Manager
Raytheon Technologies - 2 LocationsIndexed from Workday Benefit evidence checked May 7, 2026posted 187 days agoWhy we showed this
Employer: "technologies"Employer: semantic match+1
Unspecified Marketing From the posting source - Senior From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedDigital Technology Manager 2 Locations posted: Posted 30+ Days Ago
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Sr. Manager, Finance Technology & Transformation
Salesforce - Ireland - DublinIndexed from Phenom Umbraco Benefit evidence checked May 7, 2026posted 332 days agoWhy we showed this
Description: "technologies"Description: semantic match+1
Unspecified Finance From the posting source - Senior From the posting source Resolvable source Verified parental leave: 26 wksource Inferred from posting Verified non-birth-parent leave: 12 wk Salary not disclosed Equity Inferred from posting 401(k) reportedSr. Manager, Finance Technology & Transformation Ireland - Dublin The Controlership team is seeking an experienced finance technology leader to drive digital transformation initiatives and deliver innovative solutions that enhance operational efficiency, compliance, and strategic decision-making across our organization. Position Summary We are looking for an accomplished Senior Manager to join our Finance Technology and Innovation function, reporting directly to the Senior Director of Finance Technology and Innovation. This role requires a strategic thinker with deep expertise in finance operations, technology solutioning, and project delivery. The ideal candidate will have a proven track record of leveraging emerging technologies, including AI/ML, to streamline processes, reduce costs, and deliver measurable business value while collaborating closely with leadership to execute the team's vision. Strategic Leadership & Transformation Support enterprise-wide finance technology transformation initiatives that align with organizational strategic goals Collaborate with executive leadership and the Controllership Operations team to identify opportunities for technology-enabled process improvements Contribute to change management efforts to ensure smooth adoption of new technologies and processes Help execute the technology roadmap for the Controllership and broader Finance organization Technology Innovation & Implementation Evaluate, recommend, and implement cutting-edge technologies including Agents, AI/ML, automation tools, and advanced analytics platforms Manage and deliver technology projects that improve efficiency, compliance, accuracy, and operational insights Contribute to innovation programs that encourage experimentation and adoption of emerging technologies Provide insights and recommendations to senior finance leadership on technology strategy and process enhancement opportunities Team Leadership & Development Manage and mentor team members and project workstreams Foster
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Business Technology Partner Manager Process Transformation Procurement
Bunge - Sant Just DesvernIndexed from Successfactors Benefit evidence checked May 7, 2026posted 156 days agoWhy we showed this
Title: semantic matchSource-backed benefitsUnspecified Sales From the posting source - Senior From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosedBusiness Technology Partner Manager Process Transformation Procurement Sant Just Desvern Requisition Number: 44361 We are seeking a highly business‑centric Business Technology Partner Manager Process Transformation Procurement, with a primary focus on Procurement and Finance. This role serves as the strategic interface between Corporate leadership and Business Technology, ensuring that technology investments, roadmaps, and delivery outcomes are fully aligned with enterprise financial objectives, governance standards, and global operating models. The BTP is accountable for translating Procurement and Finance strategies into a clear, prioritized Business Technology roadmap; coordinating delivery through global product and technology teams; and ensuring measurable business value through agreed OKRs and performance metrics. This role partners closely with senior leaders across Procurement, Finance, Internal Controls, and Shared Services, as well as Business Technology product, architecture, and delivery teams. Main Accountabilities: Act as the primary Business Technology point of contact for Corporate Procurement and Finance leadership. Develop a deep understanding of Procurement and Finance strategies, operating models, regulatory and control requirements, and transformation priorities. Translate business strategy and functional needs into a clear, value‑driven Business Technology roadmap aligned with enterprise architecture, global standards, and investment governance. Proactively identify, propose, and drive technology‑enabled initiatives to improve Procurement an
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Technical Lead, Digital Design Subsystems
Google - Bengaluru, Karnataka, IndiaIndexed from Google Custom Benefit evidence checked May 7, 2026posted 157 days agoWhy we showed this
Description: semantic matchDescription: "technologies"+2
Unspecified Engineering From the posting source - Senior From the posting source Resolvable source Verified parental leave: 18 wksource Resolvable source Verified non-birth-parent leave: 18 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedTechnical Lead, Digital Design Subsystems Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Lead a team of ASIC RTL engineers on sub-system and activities including: plan tasks, hold code and design reviews, code development of complex features. Interact closely with the Architecture team and develop implementation (microarchitecture and coding) strategies to meet quality, schedule and Power, Performance, and Area (PPA) for sub-system integration. Work closely with the cross-functional team of Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process. Minimum qualifications: Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. 10 years of experience working on multiple SoCs with silicon success. 3 years of experience in RTL coding using Verilog or Systemverilog language. Experience in design and multi power domains with clocking. Preferred qualifications: Experience in high performance design, multi power domains with complex clocking. Proficient
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Embedded Firmware Engineer, Digital Signal Processing
Google - Sunnyvale, CA, USAIndexed from Google Custom Benefit evidence checked May 7, 2026 Comp disclosed in postingposted 163 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Mid From the posting source Resolvable source Verified parental leave: 18 wksource Resolvable source Verified non-birth-parent leave: 18 wksource $192K-$279K From the posting source Equity Inferred from posting 401(k) reportedEmbedded Firmware Engineer, Digital Signal Processing Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will architect the control-plane software for the entire high-speed Physical Layer (PHY). You will lead the development of complex state machines for link training and auto-negotiation that allow Google's AI clusters to communicate reliably at next-generation data rates. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking,
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Hardware Systems Engineer, Watches
Google - Mountain View, CA, USAIndexed from Google Custom Benefit evidence checked May 7, 2026 Comp disclosed in postingposted 158 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 18 wksource Resolvable source Verified non-birth-parent leave: 18 wksource $132K-$190K From the posting source Equity Inferred from posting 401(k) reportedHardware Systems Engineer, Watches Mountain View, CA, USA The Pixel Watch Electrical Engineering (EE) team is responsible for the end-to-end hardware development of Google's first-party Watch products. We work with product managers during initial concept and design phases, advocate new technology investigations, and manage the entire hardware lifecycle, from board integration and comprehensive validation to overseeing manufacturing to deliver products with a user experience and state-of-the-art health sensing capabilities. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $132000 - $190000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Work with internal teams to evaluate and select components for next generation products based on product goals and end-user experiences. Design, develop, and review wearable systems and sub-components from concept to mass production. Perform detailed development to bring your design to mass production by setting factory test requirements, assisting in software bring up, traveling on-site to the manufacturer to ensure the design is built and tested successfully. Create system specifications and plan/lead validation of designs. Lead complete functional verification, signal characterization, power modeling/test, and system coexistence testing. Drive resolution of cross-functional issues including those related to architecture (performance, power consumption), production (quality, failure analysis, manufacturing), and development (schematic design and review, PCB layout, and system integration). Work with and manage suppliers/manufacturing partners to establish mutually beneficial relationships for future product designs. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Physics, a related field,
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Senior Hardware Systems Engineer, Watches
Google - Mountain View, CA, USAIndexed from Google Custom Benefit evidence checked May 7, 2026 Comp disclosed in postingposted 158 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Senior From the posting source Resolvable source Verified parental leave: 18 wksource Resolvable source Verified non-birth-parent leave: 18 wksource $159K-$231K From the posting source Equity Inferred from posting 401(k) reportedSenior Hardware Systems Engineer, Watches Mountain View, CA, USA The Pixel Watch Electrical Engineering (EE) team is responsible for the end-to-end hardware development of Google's first-party Watch products. We work with product managers during initial concept and design phases, advocate new technology investigations, and manage the entire hardware lifecycle, from board integration and comprehensive validation to overseeing manufacturing to deliver products with a user experience and state-of-the-art health sensing capabilities. As an Electrical Engineer on the Watch product team, you will be responsible for key design activities throughout the Watch product development phase. This includes focusing on technical design development and optimization, collaborating with cross-functional teams, and working closely with external suppliers and partners for design and manufacturing. You will also work on some hardware related issues Failure Analysis (FA) that feedback from users, EFFA, RMA. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $159000 - $231000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Be responsible for the electrical design integration and the validation of Google's Watch products. Deliver the boards (PCBA or FPCA) by performing all the design tasks including schematic and layout, collaboration with product design, Signal Integrity and Power Integrity (SIPI), power and sub-system teams for the design optimization. Bring up the system, plan the validation, trouble shooting and conduct the measurements. Debug the issue discovered from the factory production, reliability, user trial, RMA, etc. Collaborate with Google
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Staff Business Development/ Operations Manager (Image Sensors)
Samsung Semiconductor, Inc. - San Jose, California, United StatesIndexed from Greenhouse Benefit evidence checked Jun 7, 2026 Comp disclosed in postingposted 198 days agoWhy we showed this
Description: semantic matchDescription: "technologies"+3
Unspecified Sales From the posting source - Senior From the posting source Resolvable source Verified parental leave: 8 wksource Inferred from posting Verified non-birth-parent leave: 8 wk $152K-$236K From the posting source Inferred from posting Fertility benefits Inferred from posting 401(k) reportedStaff Business Development/ Operations Manager (Image Sensors) San Jose, California, United States Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities. What You'll Do We are seeking a skilled Business Development Manager to join our dynamic team. You will be responsible for overseeing the development and implementation of cutting-edge image sensor technologies. This is a highly impactful role where you will have the opportunity to work with cross-functional teams and drive the success of our image sensor engineering programs. In this role, you will manage the entire lifecycle of image sensor projects from concept to production. You will collaborate with internal stakeholders, such as engineering, marketing, operations, and manufacturing, to ensure the timely and successful delivery of image sensor solutions. Your expertise in image sensor engineering will be crucial in providing technical guidance and ensuring the highest level of product
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Senior Manager, Finance Technology & Transformation
Salesforce - Canada - TorontoIndexed from Phenom Umbraco Benefit evidence checked May 7, 2026posted 232 days agoWhy we showed this
Description: "technologies"Description: semantic match+1
Unspecified Finance From the posting source - Senior From the posting source Resolvable source Verified parental leave: 26 wksource Inferred from posting Verified non-birth-parent leave: 12 wk Salary not disclosed Equity Inferred from posting 401(k) reportedSenior Manager, Finance Technology & Transformation Canada - Toronto The Controlership team is seeking an experienced finance technology leader to drive digital transformation initiatives and deliver innovative solutions that enhance operational efficiency, compliance, and strategic decision-making across our organization. Position Summary We are looking for an accomplished Senior Manager to join our Finance Technology and Innovation function, reporting directly to the Senior Director of Finance Technology and Innovation. This role requires a strategic thinker with deep expertise in finance operations, technology solutioning, and project delivery. The ideal candidate will have a proven track record of leveraging emerging technologies, including AI/ML, to streamline processes, reduce costs, and deliver measurable business value while collaborating closely with leadership to execute the team's vision. Strategic Leadership & Transformation Support enterprise-wide finance technology transformation initiatives that align with organizational strategic goals Collaborate with executive leadership and the Controllership Operations team to identify opportunities for technology-enabled process improvements Contribute to change management efforts to ensure smooth adoption of new technologies and processes Help execute the technology roadmap for the Controllership and broader Finance organization Technology Innovation & Implementation Evaluate, recommend, and implement cutting-edge technologies including Agents, AI/ML, automation tools, and advanced analytics platforms Manage and deliver technology projects that improve efficiency, compliance, accuracy, and operational insights Contribute to innovation programs that encourage experimentation and adoption of emerging technologies Provide insights and recommendations to senior finance leadership on technology strategy and process enhancement opportunities Team Leadership & Development Manage and mentor team members and project workstreams Foster
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Senior Photonic Engineer, Machine Learning
Google - Sunnyvale, CA, USAIndexed from Google Custom Benefit evidence checked May 7, 2026 Comp disclosed in postingposted 163 days agoWhy we showed this
Description: semantic matchDescription: "technologies"+2
Unspecified Data From the posting source - Senior From the posting source Resolvable source Verified parental leave: 18 wksource Resolvable source Verified non-birth-parent leave: 18 wksource $159K-$231K From the posting source Equity Inferred from posting 401(k) reportedSenior Photonic Engineer, Machine Learning Sunnyvale, CA, USA As a Photonic Engineer for machine learning systems, you will be responsible for creating next generation optical interconnect technologies for Tensor Processing Unit (TPU) systems. You will work with both the optics team and machine learning team to lay out the optical technology roadmaps to scale future generation machine learning systems.Our Platforms Infrastructure Engineering team designs and builds the hardware and software technologies that power all of Google's services. Our computational challenges are complex and unique, enabled by cutting-edge custom hardware designed and made in-house. As a hardware engineer, you will design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You will see those systems from concept all the way through to high-volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers, affecting millions of Google users. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $159000 - $231000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Design low-cost and high-speed optical transceivers for data center applications. Develop optical systems and architectures to scale Tensor Processing Unit (TPU) and Graphics Processing Unit (GPU) superpods. Identify, research, and evaluate emerging photonic networking technologies. Explore optical technologies to disaggregate and improve the efficiencies of future computing systems. Minimum qualifications: PhD degree in Electrical Engineering, Computer Engineering, Physics, a related field,
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Senior Hardware Engineer, Electromagnetic and SIPI, Pixel Watch
Google - Mountain View, CA, USAIndexed from Google Custom Benefit evidence checked May 7, 2026 Comp disclosed in postingposted 163 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Senior From the posting source Resolvable source Verified parental leave: 18 wksource Resolvable source Verified non-birth-parent leave: 18 wksource $159K-$231K From the posting source Equity Inferred from posting 401(k) reportedSenior Hardware Engineer, Electromagnetic and SIPI, Pixel Watch Mountain View, CA, USA In this role, you will participate actively across all lifecycle stages of Pixel Watch product development. You will serve as the technical owner for component and system-level Electromagnetic (EM) integrity, signal and power integrity translating data into actionable architecture-level insights. You will require close collaboration with cross-functional teams to predict, debug, and optimize the hardware performance of next-generation wearable technology.The Google Pixel team focuses on designing and delivering the world's most helpful mobile experience. The team works on shaping the future of Pixel devices and services through some of the most advanced designs, techniques, products, and experiences in consumer electronics. This includes bringing together the best of Google's artificial intelligence, software, and hardware to build global smartphones and create transformative experiences for users across the world. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $159000 - $231000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Lead comprehensive EM simulations at both the component and system levels, with a focus on passive mode extraction and overall system performance analysis. Perform detailed correlation studies between simulation models and bench lab measurements to ensure and maintain high-fidelity simulation accuracy. Deliver targeted simulations and DOEs (Design of Experiments) to assist cross-functional teams with EM-related debugging, root-cause analysis, and hardware optimization. Conduct Pixel Watch Signal Integrity and Power Integrity (SIPI) simulations in the frequency domain,
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Staff Hardware Systems Engineer, Watches
Google - Mountain View, CA, USAIndexed from Google Custom Benefit evidence checked May 7, 2026 Comp disclosed in postingposted 158 days agoWhy we showed this
Description: semantic matchDescription: "technologies"+2
Unspecified Engineering From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 18 wksource Resolvable source Verified non-birth-parent leave: 18 wksource $188K-$275K From the posting source Equity Inferred from posting 401(k) reportedStaff Hardware Systems Engineer, Watches Mountain View, CA, USA The Pixel Watch Electrical Engineering (EE) team is responsible for the end-to-end hardware development of Google's first-party (1P) Watch products. We work with product managers during initial concept and design phases, guide new technology investigations, and manage the entire hardware lifecycle-from board integration and comprehensive validation to overseeing manufacturing to deliver products with an advanced user experience and health sensing capabilities. We are seeking a highly skilled and visionary Electrical Engineer to lead the hardware integration and electrical architecture for our next-generation hardware. In this role, you will be the technical anchor for form factor integration, strategizing how to partition silicon into compact enclosures while maximizing power efficiency and thermal performance. You will operate at the intersection of electrical, mechanical, and systems engineering, pushing the boundaries of what is physically possible. You will be solving multi-dimensional hardware puzzles, driving architectural convergence across teams, and turning New Technology Introductions (NTIs) into mass-produced reality. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $188000 - $275000 (USD) + 20% bonus target + bonus + equity + benefits Learn more about benefits at Google . Drive end-to-end electrical architecture for space-constrained devices, leveraging advanced packaging technologies like System in Package (SIP) and rigid-flex to maximize density and minimize Z-height. Act as the technical linchpin, collaborating with mechanical, Radio Frequency (RF), sensors, and display teams to resolve physical layout collisions and foster architectural convergence. Lead data-driven trade-offs balancing
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Hardware System Architect, Pixel Watch
Google - Mountain View, CA, USA; +1 moreIndexed from Google Custom Benefit evidence checked May 7, 2026 Comp disclosed in postingposted 163 days agoWhy we showed this
Description: semantic matchDescription: "technologies"+2
Unspecified Engineering From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 18 wksource Resolvable source Verified non-birth-parent leave: 18 wksource $188K-$275K From the posting source Equity Inferred from posting 401(k) reportedHardware System Architect, Pixel Watch Mountain View, CA, USA; +1 more The Watch Hardware Engineering team is looking for a System Architect responsible for defining and implementing the hardware architecture for wearable products to enable ambient and edge computing applications. In this role, you will provide thought leadership in architecting the system design and platform architecture for next generation wearable products. The architect will ensure all subsystems work together to meet performance, power, and cost goals for all critical user journeys. This role involves an understanding and analysis of the data processing paths and associated hardware, silicon, and software solutions. You will collaborate cross-functionally both internally and externally with silicon vendors and technology partners. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $188000 - $275000 (USD) + 20% bonus target + bonus + equity + benefits Learn more about benefits at Google . Architect the data processing paths and hardware-software interfaces for ambient and edge computing applications on wearable hardware. Define system and component-level specifications for performance, power, and thermals. Support critical user journeys, including on-device AI
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