Astera Labs jobs

Staff/ Principal Physical Design CAD Engineer Tel Aviv-Yafo, Tel Aviv District, Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, We are looking for a Physical Design CAD Engineer with at least 3 years of hands-on experience in digital implementation flows. The ideal candidate is highly technical, curious, and eager to drive innovation by combining strong physical design knowledge with modern automation and GenAI-based methodologies. This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with

Principal Quality Engineer Aachen, North Rhine-Westphalia, Germany Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Principal Quality Engineer Role Summary As Principal Quality Engineer based in Aachen, you are the technical authority for quality across our optical product line and regional quality lead for European operations. You will bridge HQ (San Jose) and the Aachen manufacturing site, drive quality integration for in-house optical manufacturing, lead supplier quality for regional semiconductor and optical vendors, and support Asia-based RMA activities for in-region products. Key Responsibilities Quality ‑ System Integration: Lead ISO 9001 alignment between San Jose HQ, Aachen, and other regional locations to harmonize procedures, audit schedules, and corrective action processes across both semiconductor and optical product lines. Process Development & Implementation: Design, document, and roll out new quality processes, procedures, and work instructions needed to support emerging photonics products and manufacturing capabilities. In ‑ Process Inspection & Controls: Oversee in ‑ process inspection activities for the in ‑ house manufacturing operation, establishing SPC, go/no ‑ go

Optical Test Engineering, Senior Director San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Senior Director, Optical Test Engineering Position Overview We are seeking an experienced Senior Director of Optical Test Engineering to lead the development, validation, and manufacturing support of advanced integrated optical interconnect solutions. This role focuses on optical-electrical integration at the module level, bridging transceiver and compute platform interfaces with comprehensive test strategy and execution. Key Responsibilities Strategic Leadership - Define and execute the optical test engineering roadmap for next-generation interconnect architectures - Establish testing methodologies and standards for tightly integrated optical-electrical assemblies - Lead cross-functional teams across optical design, electrical engineering, manufacturing, and quality - Develop partnerships with ecosystem partners on test protocols and validation requirements Technical Program Management - Oversee test strategy development for optical modules with embedded or adjacently mounted optical components - Drive creation of comprehensive test plans covering optical performance, electrical performance, thermal management, and reliability - Establish acceptance criteria and performance benchmarks

Principal Mixed Signal Design Verification Engineer San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description We are looking for Principal Design Verification Engineers with proven experience in all aspects of verification in UVM and C/C++. The candidate must have experience using high level programming languages such as C/C++ to communicate with System Verilog and/or UVM based environments to aid RTL simulation, CoSimulation and Emulation. Basic qualifications: - Strong academic and technical background in electrical engineering. At minimum, a Bachelor's in EE is required, and a Maser's is preferred. - ≥8 years' experience supporting or developing complex high-speed SerDes/silicon products for Server, Storage, and/or Networking applications. - Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer meetings in advance, and to work with minimal guidance and supervision. - Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind! - Authorized to work in US and start immediately.

Principal Engineer, Analog Mixed-Signal IC Layout Bengaluru, Karnataka, India Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Overview: As an Analog Mixed-Signal IC Layout Lead Engineer, you will play a critical role in designing advanced node Bi-CMOS / CMOS products. You will be responsible for managing chip top-level layout and integration along with block level layout design and ensuring successful tapeout. You will work to build state-of-the art high speed circuits minimizing layout parasitics, while applying techniques to reduce skew and crosstalk. Meeting EM/IR compliance requirements is essential. You will ensure strict adherence to DRC, LVS, ANT, and density rules. Additionally, awareness of ESD and latch-up design practices is expected to ensure robust and reliable layout implementations. You will apply a solid foundation in device physics, along with demonstrating a strong three-dimensional understanding of device layout. You will collaborate with a dynamic, cross-functional team of analog designers and layout engineers across multiple time zones. We are looking for a highly motivated, team-oriented individual who

Technical Lead Design Verification Engineer San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . We are looking for a Technical Lead Design Verification Engineers with a flair for being a code breaker, ability to come up hybrid mechanisms for verification of complex ASICs. Experience with System Verilog, C, C++, Python or other scripting languages would be a plus. Using your coding and problem-solving skills, you will contribute to the functional verification of the designs. You'll be responsible for the full life cycle of verification, from planning to writing tests to debugging, collect and closing coverage. You'll also work with the software and system validation teams to come up with test plans and executing them in emulation platforms. Basic qualifications - Strong academic and technical background in electrical engineering. At minimum, a Bachelor's in EE is required, and a Masters is preferred. - ≥5 years' experience verifying and validating complex SoC for Server, Storage, and Networking applications. - Knowledge of industry-standard simulators, revision control

Principal DFT Engineer Tel Aviv-Yafo, Tel Aviv District, Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Principal DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters. As a Principal DFT Engineer, you will provide technical leadership across the full DFT lifecycle-from architecture and specification through implementation, verification, and silicon bring-up. You will define and drive DFT strategy, establish robust methodologies, and lead execution to ensure high test quality and manufacturability. This role requires deep expertise, cross-functional influence, and the ability to drive DFT excellence across projects and

Sr. Director of Product Marketing San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking a Senior Director of Product Marketing to lead go-to-market strategy for our industry-leading fabric switch and memory controller solutions. This is a high-impact leadership role at the intersection of technology and market strategy, where you'll shape how the world's largest hyperscalers and AI infrastructure builders understand and adopt our connectivity products. As a senior leader on the product marketing team, you'll drive positioning, messaging, and competitive strategy for products enabling the next generation of AI and cloud data centers. You'll partner closely with engineering, sales, and executive leadership to translate customers' needs into competitive roadmaps and compelling value propositions that resonate with decision-makers. This role requires someone who can move fluidly between silicon-level technical discussions and strategic market conversations. With AI infrastructure demand accelerating and Astera Labs at the forefront of solving critical connectivity bottlenecks, this is an opportunity to shape

Director, Digital Compute & Power Optimization Toronto, Ontario, Canada Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description We are looking for a hands-on Digital Design Engineering Manager to drive high-speed connectivity solutions. You will build and lead a team responsible for delivering the micro-architecture and implementation of front-end digital design, including RTL development, synthesis, IP integration, and block-level verification for high-performance ASICs. The ideal candidate should have strong experience with low-power design techniques and a solid understanding of SerDes DSP design, including equalizer optimization for power and area efficiency. The candidate must also have a good knowledge of communication and interface protocols such as CXL/PCIe (Gen 3 and above), Ethernet, or DDR. Basic qualifications: - Strong academic and technical background in electrical engineering. A Bachelor's degree in EE is required, and a Master's degree is preferred. - 10+ years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. - 5+ years' experience managing a team of RTL design engineers.

Manager, Physical Design Engineer Toronto, Ontario, Canada Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking a Physical Design Engineering Manager to lead a team of physical design engineers at our Toronto site, driving the implementation of connectivity ASICs within our Signal Connectivity Group. This group is responsible for products that enable high-speed serial connectivity including PCIe retimers, Ethernet retimers, and signal conditioning solutions deployed across the world's largest AI clusters and hyperscale data centers. As an Physical Design Manager Engineering Manager, you will combine hands-on technical leadership with people management, owning physical design execution from RTL to GDSII while building and mentoring a high-performing team. You will drive floorplanning, place-and-route, timing closure, and sign-off for complex designs requiring deep understanding of high-speed physical layer interfaces and SerDes integration at TSMC advanced nodes. This role is fully on-site at our Toronto location . Basic Qualifications - Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Master's preferred. -

Principal Integrated Circuit Designer Singapore Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . As an Integrated Circuit Designer, you will be part of a key team designing sophisticated advanced node CMOS products. Key Job Duties: - The design and development of the layout for integrated circuits according to electronics engineering principles, using software to create design schematics and diagrams. This will include [developing and verifying circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs to meet performance targets]. - The management of manufacturing process of the products, including technology yield and performance of the products. - The development of test programmes and procedures to ensure the products meet their performance specifications. This will include [working on analog and clocking blocks for connectivity applications, using industry-standard tools like Spectre and MATLAB]. - The provision of advice on aspects of semiconductor process technology and maintain and repair semiconductor process equipment. Basic Qualifications - Strong academic and technical background in electrical engineering. A Master's or

Sr. Principal Product Marketer - Leo San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking a Senior Principal, Product Marketing to serve as the strategic marketing leader for our Leo Smart Memory Extender product line - the industry's most advanced CXL-based solution enabling memory expansion and disaggregation for AI and cloud infrastructure at rack scale. This is a senior individual contributor role with outsized influence, where you'll define how the market understands, evaluates, and adopts CXL memory technology. As AI models scale to hundreds of billions of parameters and memory capacity becomes the defining bottleneck in modern data centers, Leo is uniquely positioned to unlock new levels of performance and efficiency. In this role, you'll operate as the authoritative voice of the Leo product line - shaping narratives that influence hyperscaler architecture decisions, driving industry thought leadership, and partnering with Astera Labs' most senior technical and business leaders to accelerate market creation. This is a

Production Director Aachen, North Rhine-Westphalia, Germany Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . AsteraLabs Germany GmbH, located in Aachen, is part of the connectivity group and specialized in the design and production of highly scalable fiber-to-the-chip connector solutions, based on micro-optical components. As head of the entire production department, the Director Production is responsible for the overarching definition and control of all production processes for the micro-optical connector units as well as the management of the entire production team with the aim of safe, on-time, quality- and cost-efficient series production. Location: On-Site - Aachen, North Rhine-Westphalia, Germany. Area of responsibility Job Description Operational production control - Ensuring a smooth production process in compliance with labor regulations as well as relevant quality, safety and environmental standards. - Ensuring the relevant documentation of work results, deviations and corrective actions. - Determination and analysis of relevant production key figures as well as initiation and monitoring of relevant control measures. Organization and resource planning - Operational production planning

Analog / Mixed-Signal Layout Engineer Singapore, Singapore Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . We are looking for a Analog / Mixed-Signal Layout Engineer to join our ASIC team working on the forefront of high-performance compute and networking standards in advanced CMOS process nodes. The ideal candidate will have an impeccable hardware engineering background with an emphasis on VLSI and/or computer architecture. We are looking for experience in design, verification, and validation of real-world systems. Exposure to high-speed interfaces PCIE, DDR, HBM, Serdes technologies would be great to have. Above all, curiosity and ability to learn is a must. In this position you will be responsible for design and/or verification of blocks using leading edge methodology and tools. Basic qualifications: - Pursuing BS or MS in EE/CS or related fields. - Hardware engineering background with an emphasis in VLSI or Computer Architecture. - Exposure to Digital design or verification, VLSI design and circuits, Computer Architecture. Required experience : - Hands-on and knowledge of RTL

Principal Analog Mixed-Signal Design Engineer Toronto , Canada Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description: As an Analog/Mixed-Signal IC Design Engineer, you will be part of a key team designing sophisticated advanced node CMOS products. Your responsibilities will include developing and verifying circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs to meet performance targets. You will also work on analog and clocking blocks for connectivity applications, using industry-standard tools like Spectre and MATLAB. The company seeks a highly motivated designer for this role Basic Qualifications: - Strong academic and technical background in electrical engineering. A Master's or PhD degree in EE is required, preferably from a top-tier university. - 8+ years of experience supporting or developing complex analog IC designs. Required Experience: - Hands-on experience in designing high-speed mixed-signal circuits including ADC/DAC data converters, RX front-end, TX driver/serializer, low-jitter PLLs, TX/RX calibration, low-jitter CLK distribution are other high-speed analog circuits is a must - Have a deep understanding

Physical Design/CAD Engineer San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . As an Astera Labs Physical Design/CAD Engineer you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires RTL to GDS ownership across design stages (Synthesis/PnR/STA/Signoff), deep technical expertise, and close collaboration with RTL and verification teams to ensure robust full-chip signoff. This role is fully on-site and in-person. Key Responsibilities - As Physical Design CAD Engineer you will support and build flows for world class EDA tools. - Drive various Physical Design flow related activities, ensuring robust signoff across complex SoCs or sub-systems. - Architect and recommend flow improvements and enhance existing methodology for high performance design. - Good understanding of flow development related to backend tools like Synthesis/PnR/Extraction/DRC/LVS etc. - Work with cross function teams to define requirements and specifications

Principal Product Manager - Ethernet San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Are you passionate about creating differentiated products and working with hyperscale and AI platform providers to deploy the next generation of data center infrastructure? We are seeking a highly technical and experienced product manager to join our team at Astera Labs. As a key member of our product management team, you will work closely with customers, product marketing, engineering and other internal cross-functional teams to define and deliver competitive silicon, hardware and software solutions. This is a unique opportunity to play a pivotal role in the success of our Taurus Ethernet Retimer portfolio. We are scaling our Taurus product management team to support our worldwide customers, offering ample opportunities for growth and advancement within the product team. Based in San Jose, this position requires an in-person presence with travel to customers. Key Responsibilities - Own product definition: Define detailed product requirements and prioritize features, enhancements, and bug fixes based

Finance and Administration Intern (Part-Time, Germany 2026) Aachen, North Rhine-Westphalia, Germany Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Support the finance team across accounting, procurement, financial planning, and process improvement in an international environment. Key Responsibilities - Process invoices, create POs, and support vendor onboarding - Support OPEX planning and analyze production cost structures - Contribute to financial analysis and planning activities - Assist ERP migration and improve processes - Support automation initiatives (e.g., Power Automate, AI tools) Your Profile - Student in Finance, Accounting, Business, or similar - Strong analytical skills and attention to detail - Structured, reliable, and proactive way of working - Quick learner with ability to work independently - Good Excel skills; ERP/automation tools are a plus - Fluent in English and German We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents,

Senior/ Staff Physical Design STA Engineer Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity. Key Responsibilities - Execute the STA flow and sign-off methodologies, ensuring our

Optical Validation Engineer, Tech Lead San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . We are seeking an experienced Optical (EIC/PIC) Validation Engineer at the Senior to Principal level to lead the validation, characterization, and qualification of advanced photonic integrated circuits (PICs) closely integrated with electronic integrated circuits (EICs) multiple optical configurations. This high-impact role focuses on ensuring the performance, reliability, and manufacturability of next-generation optical engines for high-speed data center, AI/ML, and telecom applications. The ideal candidate has deep expertise in electro-optical testing, system-level validation, and multiple optical integration challenges. Key Responsibilities - Lead end-to-end validation and characterization of Optical Engines integrating EIC and PIC in multiple Silicon Photonic architectures. - Develop comprehensive test plans, methodologies, and automation frameworks for optical, electrical, and electro-optical performance metrics (e.g., BER, eye diagrams, insertion loss, extinction ratio, receiver sensitivity, transmitter power). - Perform detailed characterization of key building blocks: modulators, photodetectors, lasers, waveguides, couplers, and high-speed EIC/PIC interfaces. - Validate co-packaged optics performance

Optical Test Engineer, Tech Lead San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . We are seeking a world-class Senior Staff to Principal Optical Test Engineer to lead the development and execution of advanced test strategies for Co-Packaged Optics (CPO) solutions. This senior role drives optical and electro-optical testing for next-generation high-bandwidth CPO modules and optical engines integrated with ASICs for AI, hyperscale data centers, and high-performance computing. You will architect test methodologies, develop hardware/software platforms, and enable high-volume manufacturing while ensuring world-class performance, reliability, and yield. This is a high-impact technical leadership position at the forefront of silicon photonics and co-packaged optics innovation. Key Responsibilities - Lead the definition, development, and qualification of comprehensive test solutions for CPO optical engines, including wafer-level, die-level, package-level, and system-level testing. - Design and implement optical test hardware and automation systems (e.g., active alignment, fiber array attachment, high-speed optical I/O characterization). - Develop test programs and methodologies for key photonic parameters: insertion loss, eye

Sr. Principal DSP Architect (Optical Transceivers & PAM4) San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview As a Sr. Principal DSP Architect, you will be the technical visionary leading the definition and development of next-generation Digital Signal Processing (DSP) architectures. Your focus will be on high-speed PAM4 (Pulse Amplitude Modulation 4-level) systems and coherent/direct-detect optical transceivers. You will bridge the gap between theoretical communications theory and silicon implementation, driving the roadmap for 800G, 1.6T, and beyond. Key Responsibilities - Architectural Leadership: Lead the definition of DSP micro-architecture for high-performance ASICs, focusing on low-power, high-throughput data paths. - Algorithm Development: Design, model, and simulate advanced DSP algorithms for: - Adaptive Equalization (FFE, DFE, MLSE). - Forward Error Correction (FEC). - Clock and Data Recovery (CDR). - Chromatic Dispersion (CD) and Polarization Mode Dispersion (PMD) compensation. - Modeling & Simulation: Develop bit-accurate and performance-accurate models using Python, MATLAB, or C++ to validate architectural choices against Bit Error Rate (BER) targets. - Cross-Functional

Silicon Technical Program Manager Tel Aviv-Yafo, Tel Aviv District, Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Silicon Technical Program Manager to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters. As an Technical Program Manager, you will be the key architect of our silicon's operational reality. You won't just track timelines - you will help establish our local execution culture and technical standards, owning the cross-functional journey of transforming complex logic into high-performance silicon. Key Responsibilities - Drive and manage ASIC development and subsystems from concept through to production

Principal Product Application Engineer - Leo San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . About the Role As a Principal Product Applications Engineer on the Leo team, you will sit at the intersection of firmware engineering and customer-facing technical engagement. You will be a key technical resource for enabling Leo CXL Smart Memory Controllers at hyperscale customers and OEM partners - owning firmware bring-up, validation, and customer issue resolution from early silicon through production ramp. Firmware is considered equally important to hardware at Astera Labs, and this role reflects that. You will work directly with customers to ensure their needs are fully understood and translated into firmware solutions, while collaborating closely with the internal firmware, hardware, and systems engineering teams. This position is required onsite in San Jose, CA. Key Responsibilities - Lead firmware-focused customer engagements for Leo CXL Smart Memory Controllers, including bring-up support, feature enablement, and issue triage on customer platforms - Develop, validate, and debug firmware using