Optical Validation Engineer, Tech Lead
Astera Labs - San Jose, California, United States
Posted May 28, 2026
Benefits
- Parental leave
- Not verified
- Non-birth-parent leave
- Not verified
- Family-building benefits
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- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
- Not verified
- Relocation assistance
- Not verified
- Childcare support
- Not verified
- Learning budget
- Not verified
- Verification
- Not verified checked Jun 7, 2026
- Salary
- Not verified
- 401(k) match
- Reported from DOL Form 5500 industry filing (not employer-specific)
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Market context
- U.S. role benchmark (BLS OEWS)
- $111,944 U.S. median for this role
- Projected growth (BLS Employment Projections)
- +13.7% - Much faster than average
Matched to SOC 15-1252 - Data and ML aggregate by role bucket.
Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.
Schedule
- Shift type
- Not verified
- Weekend work
- Not verified
Company
- Equity
- Offered Verified - SEC 10-K source
Application
- Cover letter
- Not verified
- Assessment
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- Deadline
- Not stated
Where they hire
State eligibility is not yet verified.
About this role
Optical Validation Engineer, Tech Lead San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . We are seeking an experienced Optical (EIC/PIC) Validation Engineer at the Senior to Principal level to lead the validation, characterization, and qualification of advanced photonic integrated circuits (PICs) closely integrated with electronic integrated circuits (EICs) multiple optical configurations. This high-impact role focuses on ensuring the performance, reliability, and manufacturability of next-generation optical engines for high-speed data center, AI/ML, and telecom applications. The ideal candidate has deep expertise in electro-optical testing, system-level validation, and multiple optical integration challenges. Key Responsibilities - Lead end-to-end validation and characterization of Optical Engines integrating EIC and PIC in multiple Silicon Photonic architectures. - Develop comprehensive test plans, methodologies, and automation frameworks for optical, electrical, and electro-optical performance metrics (e.g., BER, eye diagrams, insertion loss, extinction ratio, receiver sensitivity, transmitter power). - Perform detailed characterization of key building blocks: modulators, photodetectors, lasers, waveguides, couplers, and high-speed EIC/PIC interfaces. - Validate co-packaged optics performance
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