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  • Network Architect

    Vodafone Group - MILANO, Milano, Italy
    Indexed from Eightfold Benefit evidence checked Jun 7, 2026
    posted 156 days ago

    Why we showed this

    Role: semantic match
    Unspecified Engineering From the posting source - Mid From the posting source Salary not disclosed Inferred from posting 401(k) reported

    Network Architect MILANO, Milano, Italy

  • Director, Digitized Case Processing & Digital Adverse Event Interfaces

    Bristol Myers Squibb - Uxbridge - GB
    Indexed from Workday Benefit evidence checked Jun 7, 2026
    posted 186 days ago

    Why we showed this

    Description: "interface"Title: "interface"
    Unspecified Marketing From the posting source - Staff Plus From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Director, Digitized Case Processing & Digital Adverse Event Interfaces Uxbridge - GB posted: Posted 30 Days Ago

  • Custody Product Development - Core banking - interfaces /integration - AVP

    State Street Corporation - Hyderabad, India
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 165 days ago

    Why we showed this

    Description: "interface"Title: "interface"
    Unspecified Engineering From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Custody Product Development - Core banking - interfaces /integration - AVP Hyderabad, India posted: Posted 9 Days Ago

  • IE- AMHS/ LAYOUT/ OI ENIGNEER

    Micron Technology, Inc. - Miaoli - Tongluo, Taiwan
    Indexed from Workday Benefit evidence checked Jun 7, 2026
    posted 178 days ago

    Why we showed this

    Role: semantic match
    Unspecified Other - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    IE- AMHS/ LAYOUT/ OI ENIGNEER Miaoli - Tongluo, Taiwan posted: Posted 22 Days Ago

  • Stage - Ingénieur 4_6mois, déploiement interface d'execution d'experiences automatisée F/H

    STMicroelectronics - Crolles, France
    Indexed from Eightfold Benefit evidence checked Jun 7, 2026
    posted 156 days ago

    Why we showed this

    Description: "interface"Title: "interface"
    Unspecified Other - Mid From the posting source Salary not disclosed Inferred from posting 401(k) reported

    Stage - Ingénieur 4_6mois, déploiement interface d'execution d'experiences automatisée F/H Crolles, France

  • Principal Engineer - IP Verification

    Indexed from Workday Benefit evidence checked May 7, 2026
    posted 156 days ago

    Why we showed this

    Role: semantic match
    Unspecified Data From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reported

    Principal Engineer - IP Verification Noida posted: Posted Today

  • UI designer

    Autodesk - Tel Aviv, ISR
    Indexed from Workday Benefit evidence checked Jun 7, 2026
    posted 187 days ago

    Why we showed this

    Role: semantic match
    Unspecified Design From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    UI designer Tel Aviv, ISR posted: Posted 30+ Days Ago

  • High-Speed I/F Subsystem Design Engineer

    Renesas Electronics - Kodaira, , Japan
    Indexed from Smartrecruiters Benefit evidence checked Jun 7, 2026
    posted 158 days ago

    Why we showed this

    Description: "interface"
    Unspecified Data From the posting source - Mid From the posting source Salary not disclosed Inferred from posting 401(k) reported

    High-Speed I/F Subsystem Design Engineer Kodaira, , Japan Company Description: Job Description: 【Background of the Recruitment】 As automotive electrification and intelligence continue to advance, automotive SoCs have become a core technology that directly supports vehicle performance and functionality. The R-Car series has evolved as a large-scale automotive SoC through the advanced integration of a wide range of IPs, including CPU, high‑speed interfaces, memory, AI/video, functional safety, and security. Among these technologies, high‑speed SerDes interfaces such as PCIe and CSI and DP and UCIe play a critical role in overall system performance and reliability. As interface speeds continue to increase and system complexity grows, ensuring quality through thorough silicon‑level evaluation and signal integrity verification has become increasingly important. In this context, we are seeking a technical leader who has hands‑on experience in high‑speed SerDes interface evaluation and can work closely with design teams and IP vendors to lead evaluation activities from a technical standpoint. By taking ownership of evaluation and contributing technical judgment to development, this role is expected to play a key part in improving the overall quality of our automotive SoCs. 【Job Description】 Lead the technical execution of high‑speed SerDes interface evaluation for automotive SoCs (R-Car series), covering interfaces such as PCIe, CSI, DP, UCIe, SerDes PHY, and other high‑speed I/F as applicable. Drive evaluation activities including silicon/board-level testing, signal integrity/quality assessment, stress testing, and standards/compliance confirmation, ensuring interface quality and robustness. Define and align evaluation strategy, organize test items, and consolidate evaluation results into actionable outputs for stakeholders.

  • Junior Layout Engineer

    NXP Semiconductors - Catania
    Indexed from Workday Benefit evidence checked May 7, 2026
    posted 187 days ago

    Why we showed this

    Role: semantic match
    Unspecified Data From the posting source - Entry From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reported

    Junior Layout Engineer Catania posted: Posted 30+ Days Ago

  • IT Software Engineer (EHS/LIMS interfaces, HL7, CorePoint engine)

    Eurofins Scientific - Belo Horizonte, MG, Brazil
    Indexed from Smartrecruiters Benefit evidence checked Jun 7, 2026
    posted 158 days ago

    Why we showed this

    Description: "interface"Title: "interface"
    Unspecified Engineering From the posting source - Mid From the posting source Salary not disclosed Inferred from posting 401(k) reported

    IT Software Engineer (EHS/LIMS interfaces, HL7, CorePoint engine) Belo Horizonte, MG, Brazil Company Description: Eurofins Scientific is an international life sciences company, providing a unique range of analytical testing services to clients across multiple industries, to make life and our environment safer, healthier and more sustainable. From the food you eat, to the water you drink, to the medicines you rely on, Eurofins laboratories work with the biggest companies in the world to ensure the products they supply are safe, their ingredients are authentic and labelling is accurate. The Eurofins network of companies believes that it is a global leader in food, environment, pharmaceutical and cosmetic product testing and in discovery pharmacology, forensics, advanced material sciences and agroscience contract research services. It is also one of the market leaders in certain testing and laboratory services for genomics, and in the support of clinical studies, as well as in biopharma contract development and manufacturing. It also has a rapidly developing presence in highly specialised and molecular clinical diagnostic testing and in-vitro diagnostic products. The group's key figures are approximately: Turnover of 6.5 billion euros, more than 940 laboratories in 62 countries and around 62,000 employees. Job Description: Essential Duties and Responsibilities: Architect, develop, implement and support/maintain interfaces that enable the exchange of patient and lab data between hospital systems (such as HIS and EHR) and laboratory information management systems (LIMS). Productivity expectations for a Corepoint Interface Engineer include: Development of 3-4 concurrent interface projects, 10-15 projects yearly. Complete an interface project

  • Head of Data

    Overwolf - Overwolf's lair
    Indexed from Custom Structured
    posted 158 days ago

    Why we showed this

    Role: semantic match
    Unspecified Data From the posting source - Staff Plus From the posting source Salary not disclosed

    Head of Data Overwolf's lair Head of Data

  • UI/UX Engineer

    Leidos - San Diego, CA
    Indexed from Workday Benefit evidence checked May 7, 2026
    posted 180 days ago

    Why we showed this

    Role: semantic match
    Unspecified Data From the posting source - Mid From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reported

    UI/UX Engineer San Diego, CA posted: Posted 24 Days Ago

  • UI Technical Designer

    thatgamecompany - Remote - US, Los Angeles, California, United States
    Indexed from Ashby Comp disclosed in posting
    posted 362 days ago

    Why we showed this

    Description: "interface"
    Remote From the posting source Design From the posting source - Mid From the posting source $84K-$148K From the posting source Inferred from posting Mental health support Unknown provenance 401(k) reported

    UI Technical Designer Remote - US, Los Angeles, California, United States UI Technical Designer Remote - US At thatgamecompany, we strive to create beautiful and intuitive UI, which embraces and contributes to the emotional experiences of our games. Our company is known for having a distinct perspective on what games can be, and crafting unique experiences that players can't find elsewhere as a result; our approach to UI is no different. Our mission is to take risks in our designs, to break new ground with solutions that players haven't seen before, and are hand-tailored towards the unique goals of our games. We are looking for a talented UI Technical Designer to join our UI team. This individual will collaborate with the rest of our UI team, along with art, design, and engineering teams to craft attractive, minimal interfaces. The ideal candidate will have exceptional UI art and design skills, with a passion for developing new interfaces from scratch, along with doing polish passes on pre-existing interfaces and wireframes. They should be confident in contributing in all disciplines required to execute on a UI design- from creating wireframes, to designing highly polished mockups, to implementing the final product in code. Responsibilities: - Work closely with the rest of the UI team to develop intuitive, beautiful, innovative interfaces for our games - Conceptualize new interfaces to solve design problems, and make new features possible - Create wireframes, mockups, and animations to drive development - Do polish passes on pre-existing interfaces and wireframes,

  • UI/UX Designer

    CACI - 2 Locations
    Indexed from Workday Benefit evidence checked Jun 7, 2026
    posted 156 days ago

    Why we showed this

    Role: semantic match
    Unspecified Design From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    UI/UX Designer 2 Locations posted: Posted Today

  • Design Engineer

    Cohu Inc - Philippines
    Indexed from Oracle Recruiting Cloud Benefit evidence checked Jun 13, 2026
    posted 170 days ago

    Why we showed this

    Description: "interface"
    Unspecified Engineering From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Design Engineer Philippines Designs, develops, layouts, documents and supervises manufacturing, testing and application of kits and handler interface solutions. Interfaces with customer, supplier, sales and customer service engineer and team members with minimal guidance.

  • Senior Project Interface Engineer – Offshore FEED Project

    KBR, Inc. - Abu Dhabi, United Arab Emirates
    Indexed from Workday Benefit evidence checked Jun 7, 2026
    posted 186 days ago

    Why we showed this

    Description: "interface"Title: "interface"
    Unspecified Data From the posting source - Senior From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Senior Project Interface Engineer – Offshore FEED Project Abu Dhabi, United Arab Emirates posted: Posted 30 Days Ago

  • Data Engineer

    Addepar - Edinburgh, UK
    Indexed from Custom Structured Benefit evidence checked Jun 7, 2026
    posted 194 days ago

    Why we showed this

    Role: semantic match
    Unspecified Data From the posting source - Mid From the posting source Salary not disclosed Inferred from posting 401(k) reported

    Data Engineer Edinburgh, UK Data Engineer

  • Sr Integrations Engineer

    Tyler Technologies - Location not specified
    Indexed from Jobvite Benefit evidence checked Jun 7, 2026
    posted 158 days ago

    Why we showed this

    Role: semantic match
    Unspecified Data From the posting source - Senior From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Sr Integrations Engineer Sr Integrations Engineer

  • posted 187 days ago

    Why we showed this

    Description: "interface"Title: "interface"
    Unspecified Other - Staff Plus From the posting source Salary not disclosed

    Post-Doctoral Fellow - Interface of Cognitive and Motor Neuroscience - Lab of Dr. Wong Montgomery County, PA posted: Posted 30+ Days Ago

  • Intern - Engineering

    Analog Devices - Thailand, Chon Buri
    Indexed from Workday Benefit evidence checked May 7, 2026
    posted 158 days ago

    Why we showed this

    Role: semantic match
    Unspecified Data From the posting source - Entry From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reported

    Intern - Engineering Thailand, Chon Buri posted: Posted 2 Days Ago

  • Joint Interface Control Officer (JICO)

    CAE Inc. - USA-NC-Fort Bragg AAF 2449 Surveyor St
    Indexed from Workday
    posted 167 days ago

    Why we showed this

    Description: "interface"Title: "interface"
    Unspecified Finance From the posting source - Mid From the posting source Salary not disclosed

    Joint Interface Control Officer (JICO) USA-NC-Fort Bragg AAF 2449 Surveyor St posted: Posted 11 Days Ago

  • Software Engineer, Human Data Interface

    Anthropic - San Francisco, CA | New York City, NY
    Indexed from Greenhouse Comp disclosed in posting
    posted 282 days ago

    Why we showed this

    Description: "interface"Title: "interface"
    Unspecified Engineering From the posting source - Mid From the posting source $320K-$405K From the posting source Equity

    Software Engineer, Human Data Interface San Francisco, CA | New York City, NY About Anthropic Anthropic's mission is to create reliable, interpretable, and steerable AI systems. We want AI to be safe and beneficial for our users and for society as a whole. Our team is a quickly growing group of committed researchers, engineers, policy experts, and business leaders working together to build beneficial AI systems. About the Role Anthropic's Human Data Interfaces team builds the systems that collect data to improve our models. This includes novel interfaces for data vendors, tooling, and front-end and back-end infrastructure that enables researchers to gather high-quality data at scale. As a Software Engineer, you'll own the architecture and execution of our data collection pipelines - designing systems that are both performant at scale and resilient to the rapidly changing needs of our research teams. You'll work closely with researchers, our cross-functional data operations partners, and the crowdworkers and vendors who use these tools day-to-day. Responsibilities: - Architect and build data collection pipelines that support rapid iteration, balancing data quality and system maintainability - Think deeply about the experience of the crowdworkers and vendors using these systems, building interfaces that are clear, efficient, and lead to high-quality data - Collaborate closely with research teams to understand evolving data needs and iterate quickly on collection methods - Partner with our Human Data Operations team to understand the end-to-end data workflow and design interfaces that make their jobs easier - Prioritize and juggle multiple workstreams, making

  • Firmware Engineer

    Fuse Energy - Location not specified
    Indexed from Workable
    posted 279 days ago

    Why we showed this

    Role: semantic match
    Unspecified Data From the posting source - Mid From the posting source Salary not disclosed

    Firmware Engineer

  • Signal Integrity Engineer – Memory Interface

    Apple - San Francisco Bay Area, United States of America
    Indexed from Apple Custom Benefit evidence checked Jun 13, 2026 Comp disclosed in posting
    posted 369 days ago

    Why we showed this

    Description: "interface"Title: "interface"
    Unspecified Engineering From the posting source - Mid From the posting source $172K-$302K From the posting source Equity Inferred from posting 401(k) reported

    Signal Integrity Engineer – Memory Interface San Francisco Bay Area, United States of America In this position, you will work with the team that develops SOCs used within Apple's mobile devices. You will be specifically responsible for memory interface signal integrity for Apple SoCs, covering the span from package to board. Prior design and modeling experience with DDR or LPDDR interfaces are a must-have. • You will work on electrical and physical design of memory systems. • Work on electrical extraction and validation of package and MLB. • Work with circuit and controller team to optimize memory system design. • Work on SI and PI modeling, simulation, and characterization memory interface. • Develop and execute test plans to validate signal and power integrity. • Work with product engineering and system engineering to debug and to improve product yield. Conduct end-to-end signal integrity and power integrity simulation studies of memory system including modeling of channels and power delivery networks of die/interposer/PKG/PCB/PMU to meet tight timing and voltage spec. Provide feedbacks and guidelines to silicon floorplan, package, system design, and other cross-functional teams. Provide optimal IO settings and design guideline to cross-functional teams. Perform feasibility study for next generation of signaling scheme. Perform correlation between simulation and silicon measurement. Minimum Qualifications: BS + 10 years of industry experience. Preferred Qualifications: MSEE + 8 years of industry experience and or Ph.D. preferred. We are looking for someone who is familiar with signal and power integrity issues of memory interfaces. Prior experience working with

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