High-Speed I/F Subsystem Design Engineer

Benefits

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Not verified checked Jun 7, 2026

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401(k) match

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Market context

U.S. role benchmark (BLS OEWS)

$111,944 U.S. median for this role

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

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Seniority

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Weekend work

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About this role

High-Speed I/F Subsystem Design Engineer Kodaira, , Japan Company Description: Job Description: 【Background of the Recruitment】 As automotive electrification and intelligence continue to advance, automotive SoCs have become a core technology that directly supports vehicle performance and functionality. The R-Car series has evolved as a large-scale automotive SoC through the advanced integration of a wide range of IPs, including CPU, high‑speed interfaces, memory, AI/video, functional safety, and security. Among these technologies, high‑speed SerDes interfaces such as PCIe and CSI and DP and UCIe play a critical role in overall system performance and reliability. As interface speeds continue to increase and system complexity grows, ensuring quality through thorough silicon‑level evaluation and signal integrity verification has become increasingly important. In this context, we are seeking a technical leader who has hands‑on experience in high‑speed SerDes interface evaluation and can work closely with design teams and IP vendors to lead evaluation activities from a technical standpoint. By taking ownership of evaluation and contributing technical judgment to development, this role is expected to play a key part in improving the overall quality of our automotive SoCs. 【Job Description】 Lead the technical execution of high‑speed SerDes interface evaluation for automotive SoCs (R-Car series), covering interfaces such as PCIe, CSI, DP, UCIe, SerDes PHY, and other high‑speed I/F as applicable. Drive evaluation activities including silicon/board-level testing, signal integrity/quality assessment, stress testing, and standards/compliance confirmation, ensuring interface quality and robustness. Define and align evaluation strategy, organize test items, and consolidate evaluation results into actionable outputs for stakeholders.

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