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Signal Integrity Engineer – Memory Interface

Apple - San Francisco Bay Area, United States of America

Posted Nov 11, 2025

Benefits

Parental leave
Not verified
Non-birth-parent leave
Not verified
Family-building benefits
  • Fertility benefits: Not verified
  • Adoption assistance: Not verified
  • Surrogacy assistance: Not verified
Mental health support
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Relocation assistance
Not verified
Childcare support
Not verified
Learning budget
Not verified
Verification
Not verified checked Jun 13, 2026
Salary
$172K-$302K From the posting source checked Jun 20, 2026
401(k) match
Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)
$116,543 U.S. median for this role
Projected growth (BLS Employment Projections)
+9.8% - Much faster than average

103% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function
Engineering From the posting source checked Jun 20, 2026
Seniority
Mid From the posting source checked Jun 20, 2026

Schedule

Shift type
Not verified
Weekend work
Not verified

Company

Equity
Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter
Not verified
Assessment
Not verified
Deadline
Not stated

Where they hire

State eligibility is not yet verified.

About this role

Signal Integrity Engineer – Memory Interface San Francisco Bay Area, United States of America In this position, you will work with the team that develops SOCs used within Apple's mobile devices. You will be specifically responsible for memory interface signal integrity for Apple SoCs, covering the span from package to board. Prior design and modeling experience with DDR or LPDDR interfaces are a must-have. • You will work on electrical and physical design of memory systems. • Work on electrical extraction and validation of package and MLB. • Work with circuit and controller team to optimize memory system design. • Work on SI and PI modeling, simulation, and characterization memory interface. • Develop and execute test plans to validate signal and power integrity. • Work with product engineering and system engineering to debug and to improve product yield. Conduct end-to-end signal integrity and power integrity simulation studies of memory system including modeling of channels and power delivery networks of die/interposer/PKG/PCB/PMU to meet tight timing and voltage spec. Provide feedbacks and guidelines to silicon floorplan, package, system design, and other cross-functional teams. Provide optimal IO settings and design guideline to cross-functional teams. Perform feasibility study for next generation of signaling scheme. Perform correlation between simulation and silicon measurement. Minimum Qualifications: BS + 10 years of industry experience. Preferred Qualifications: MSEE + 8 years of industry experience and or Ph.D. preferred. We are looking for someone who is familiar with signal and power integrity issues of memory interfaces. Prior experience working with

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