Signal Integrity Engineer – Memory Interface

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Not verified last checked Jun 13, 2026

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401(k) match

Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

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About this role

Signal Integrity Engineer – Memory Interface San Francisco Bay Area, United States of America In this position, you will work with the team that develops SOCs used within Apple's mobile devices. You will be specifically responsible for memory interface signal integrity for Apple SoCs, covering the span from package to board. Prior design and modeling experience with DDR or LPDDR interfaces are a must-have. • You will work on electrical and physical design of memory systems. • Work on electrical extraction and validation of package and MLB. • Work with circuit and controller team to optimize memory system design. • Work on SI and PI modeling, simulation, and characterization memory interface. • Develop and execute test plans to validate signal and power integrity. • Work with product engineering and system engineering to debug and to improve product yield. Conduct end-to-end signal integrity and power integrity simulation studies of memory system including modeling of channels and power delivery networks of die/interposer/PKG/PCB/PMU to meet tight timing and voltage spec. Provide feedbacks and guidelines to silicon floorplan, package, system design, and other cross-functional teams. Provide optimal IO settings and design guideline to cross-functional teams. Perform feasibility study for next generation of signaling scheme. Perform correlation between simulation and silicon measurement. Minimum Qualifications: BS + 10 years of industry experience. Preferred Qualifications: MSEE + 8 years of industry experience and or Ph.D. preferred. We are looking for someone who is familiar with signal and power integrity issues of memory interfaces. Prior experience working with

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