Advanced Micro Devices jobs

CPU Power Management Microarchitect/RTL Engineer Santa Clara, United States of America Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want to join us in these pursuits? Join us to help deliver the next groundbreaking Apple product! Apple's Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that power our innovative products, including the iPhone, iPad, Watch, Vision Pro, and Mac. We are looking for an experienced engineer to help drive architecture and RTL for world-class CPU power management solutions. As a CPU Power Management Microarchitect/RTL Engineer, you will own or contribute to the following: • Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification • RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification • Performance exploration and correlation - explore high-performance strategies and work with the performance verification

CPU Microarchitect/RTL Engineer Santa Clara, United States of America Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products! Apple's Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that power our innovative products, including the iPhone, iPad, Watch, Vision Pro, and Mac. We are looking for an experienced engineer who can drive CPU multi-level cache subsystem architecture and RTL development for multi-processor systems. As a CPU Microarchitect/RTL Engineer, you will participate in the following: • Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification • RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for formal verification • Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance • Design delivery - work

CPU ML Microarchitect/RTL Engineer Santa Clara, United States of America Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products! Apple's Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that power our innovative products, including the iPhone, iPad, Watch, Vision Pro, and Mac We are looking for an experienced engineer to drive CPU machine-learning accelerator architecture and RTL development for Apple Silicon. As a CPU ML Microarchitect/RTL Engineer, you will own or participate in the following: • Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification • RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification • Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance • Design delivery

Senior Semiconductor Laser Device Engineer Livermore, CA, United States Company Description: Join us and make YOUR mark on the World! Lawrence Livermore National Laboratory (LLNL) has turned bold ideas into world-changing impact advancing science and technology to strengthen U.S. security and promote global stability. Our mission spans four critical national security areas nuclear deterrence, threat preparedness, energy security, and multi-domain defense empowering teams to take on the toughest challenges of today and tomorrow. With a culture built on innovation and operational excellence, LLNL is a place where your expertise can make a real impact. Job Description: We have an opening for a Senior Semiconductor Laser Device Engineer with expertise in semiconductor laser diodes. You will define, develop, and deploy high power laser diodes and diode arrays. You will have an advanced understanding of semiconductor optoelectronics, micro-optics, and thermal management to specify, design, and oversee deployment of high-power laser diode arrays and work to determine requirements, set specifications and address array technology options including thermal management and electronic drivers. You will work with LLNL team members to expand the vision for continued development of diode laser technology. This position is in the Laser Systems Engineering & Operations (LSEO) Division of the Engineering Directorate. You will Operate under consultative direction with substantial authority, using in-depth analysis and subject matter expertise in highly advanced concepts, to resolve a diverse range of highly complex problems, independently determine strategies, modify approaches, and pursue actions that impact organizational operations or directions and achieve long-term goals. Provide

Senior Advanced Manufacturing Engineer - Electronics Job Location (country) United States Lear For You We work hard for the people who work for us. We champion our teams. We foster collaboration, inclusion, respect and excellence. What we are trying to say is we want to be more for you. We are your path to a better career, a better future, and a better you. Our teams have invented groundbreaking technologies, flawlessly manufactured millions of products and earned a long list of awards. Year after year, we are one of the World's Most Admired Companies. Our teams are the secret to our success. They are empowered, inventive and inclusive. Passionate about their craft. Driven to succeed. Because we all understand that we must work together to win. Are you ready for a better career? A better future? We're Lear For You. SENIOR ADVANCED MANUFACTURING ENGINEER - GLOBAL ELECTRONICS SOUTHFIELD, MICHIGAN - WORLD HEADQUARTERS As a member of the Advanced Manufacturing Engineering team, the Senior Advanced Manufacturing Engineer will be responsible for supporting cost estimation, new product launch and leading standardization and innovation initiatives. The Role: Your work will include, but not be limited to: Developing manufacturing processes and related equipment for new electrical components (SMT, Final Assembly and EOL Test). Lead cost estimation effort for new/modified business quoting. Support the analysis of work force utilization, space requirements, material flow, and leads the optimization of layout design for maximum efficiency. Expected to be able to conceptualize

Apple GPU Compiler Backend/Research Engineer, Graphics, Game and ML Cupertino, United States of America In this role, you will have the opportunity to work on defining the roadmap for Apple GPU architecture and unleash the potential for new applications. You will work cross-functionally with several hardware and software teams to prototype compiler feature support, code generation and a slew of optimizations. You will be responsible to evaluate the efficacy of the proposed changes and provide feedback. Your work will have tremendous impact across all Apple devices. We in the GPU compiler team have a strong track record of delivering optimal solutions for Apple Silicon GPUs. We have built synergies with hardware and software teams to explore and implement these solutions from conception, to prototyping to finally productizing and shipping. We strongly believe that being involved from concept allows us to unlock the true potential of new GPU architectures. We are seeking a highly skilled Compiler Backend Research Engineer to join our team. The role involves researching, designing, prototyping and implementing Apple GPU compiler optimizations to improve performance and functionality across all Apple devices. The GPU that you will work on will be shipped in every Apple device with a GPU. You will work on an LLVM-based compiler backend to generate optimized GPU binaries for future Apple Silicon GPUs that run graphics and compute workloads. In this role you will engage and collaborate with architects and micro-architects to explore and advance features and capabilities of the Apple Silicon GPUs. You will

Warehouse Assistant Ingram Micro Warehouse – Lima posted: Posted 30+ Days Ago

Executive Coordinator Ingram Micro Office – San Borja posted: Posted 11 Days Ago

Senior Engineer - NAND CMOS Device Fab 10N/X, Singapore posted: Posted 30+ Days Ago

MEMS/Microfluidic Fab Yield Improvement Engineer Singapore, South West, Singapore

Medical Laboratory Scientist I - Micro Tampa, FL, United States Medical Laboratory Scientist I - Micro

CPU Microarchitect/RTL Engineer - Fetch, Out of Order Santa Clara, United States of America Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want to join us in these pursuits? Join us to help deliver the next groundbreaking Apple product! Apple's Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that power our innovative products, including the iPhone, iPad, Watch, Vision Pro, and Mac. We are looking for an experienced engineer to drive architecture and RTL development of CPU front-end and/or out-of-order subsystem for our performant cores. As a CPU Microarchitect/RTL Engineer, you will own or participate in the following: • Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification • RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification • Performance exploration and correlation - explore high-performance strategies and

Microfabrication Engineer (R&D) Fremont, California, United States About Neuralink: We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. Team Description: The Microfabrication Team, a division of the Brain Interfaces Hardware Department, designs, manufactures, and verifies the thin-film microelectrode array that records and relays neural signals to the body of the implant. The team operates at an in-house cleanroom facility in Fremont, with operations expanding to Austin in the near future. Job Description and Responsibilities: The Microfabrication Engineer at Neuralink will be responsible for the development of micro-fabricated medical devices including thin-film microelectrode arrays used in preclinical and clinical studies within Neuralink. This includes developing process modules to push design and fabrication limits; performing metrology to monitor, test, and characterize in-process progress; and providing detailed documentation of process steps, changes, and measurements. - Design and physically realize next-generation thin-film microelectrode arrays. - Develop and deploy advanced process integration schemes for thin-film fabrication within production environments. - Execute benchtop experiments to characterize the relationship between fabrication parameters, design, and product performance (e.g., impedance and longevity). - Utilize statistical analysis on experimental data to drive data-informed product improvement decisions. - Sponsor in vivo studies to validate the physiological performance of novel designs and processes. - Author comprehensive SOPs and technical documentation to standardize process activities across the team. - Provide technical training and mentorship to team

Hardware/ Software Co-Design Engineer Austin, Texas, United States; Fremont, California, United States About Neuralink: We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. Job Description & Responsibilities: Our Hardware/ Software Co-Design Engineer will be responsible for delivering micro-architecture and register-transfer level (RTL) implementation of digital IPs and systems with a focus in high-throughput low-power digital signal processor (DSP) and general-purpose hardware accelerators towards realizing state-of-the-art brain-computer interfaces. Relevant product development experience in micro-architecture design for low-power processors, on-chip bus and network interfaces, audio/video compression processors, AI/ML accelerators, and communication PHY/MAC will be preferred. - Micro-architecture design and RTL implementation of: - Low-power digital signal processors - Low-power general-purpose hardware accelerators - Low-power graphics processing units - Low-power radio MAC/PHY - Low-power serial link MAC/PHY - Design and optimization of hardware/software interface with firmware engineers - Application-specific architecture optimization including: - Complex system modeling for energy and performance benchmarks - Workload analysis and modeling - Energy/performance profiling and analysis - Leveraging architecture-level design trade-offs with process technology and workload type - Balancing cost and performance

MEMS Layout Engineer P2 US, MA, Wilmington posted: Posted Today

Analog ASIC Architect Austin Metro Area, United States of America Design, develop, and deliver the world's most advanced mixed-signal ASICs - silicon that powers Apple's most iconic products at a scale no other company can match. Apple's Touch Technology team is at the forefront of analog and mixed-signal ASIC innovation, building high-complexity, high-volume chips that enable the world's best multi-touch experience across iPhone, iPad, Mac, and more. If you want to architect silicon that ships in hundreds of millions of devices and sets the standard for the industry, this is your team. As an Analog ASIC Architect on the Touch Technology team, you will own the architecture of complex mixed-signal ASICs from concept through silicon, with the goal of enabling best-in-class touch sensing experiences across Apple's product line. You will translate high-level system requirements into rigorous, realizable designs - defining the analog front-end architecture, signal processing pipeline, and system-level performance targets that guide the full IC development process. This is a highly cross-functional role requiring both deep technical expertise and the ability to communicate and collaborate across circuit design, digital architecture, software, and product teams. You will be expected to drive architectural decisions with clarity and conviction, grounded in first principles and shaped by a thorough understanding of the constraints and trade-offs inherent in high-volume silicon development. Define and develop analog front-end (AFE) and mixed-signal ASIC architectures for high-performance, low-power touch sensing applications Author detailed micro-architecture specifications, performance analyses, and characterization plans that serve as the technical foundation for IC

Digital IC Design Engineer Austin, Texas, United States; Fremont, California, United States About Neuralink: We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. Job Description & Responsibilities: Our Digital IC Design Engineer will be responsible for delivering micro-architecture and register-transfer level (RTL) implementation of digital IPs and systems with a focus in high-throughput low-power digital signal processor (DSP) and general-purpose hardware accelerators towards realizing state-of-the-art brain-computer interfaces. Relevant product development experience in micro-architecture design for low-power processors, on-chip bus and network interfaces, audio/video compression processors, AI/ML accelerators, and communication PHY/MAC will be preferred. - Micro-architecture design and RTL implementation of: - Low-power digital signal processors - Low-power general-purpose hardware accelerators - Low-power graphics processing units - Low-power radio MAC/PHY - Low-power serial link MAC/PHY - Design and optimization of hardware/software interface with firmware engineers - Application-specific architecture optimization including: - Complex system modeling for energy and performance benchmarks - Workload analysis and modeling - Energy/performance profiling and analysis - Leveraging architecture-level design trade-offs with process technology and workload type - Balancing cost and performance

SerDes Micro Architect Cupertino, United States of America Analog Mixed-Signal (AMS) Team is seeking a self-motivated SERDES Micro Architect to drive the definition of our next generation IPs. The SERDES IPs will be used in Apple silicon offering breakthrough power and performance for iPhone, iPad, Mac, and Apple Watch. You will define the Micro Architecture of analog mixed-signal IPs with emphasis on SERDES design. You will review firmware code, analog and digital circuits and will verify that the design meets performance requirements. You will work with silicon evaluation and design verification teams to define expected behavior. You would lead the debug effort in system bring up and factory test. You will work with signal integrity engineers to determine system requirements. Minimum Qualifications: BS degree in technical discipline with minimum 10 years of relevant experience. Preferred Qualifications: Experience leading the definition of high-speed SERDES receiver, transmitter, and clocking blocks Deep understanding of adaptation and optimization algorithms Deep understanding of communications and information theory Proficiency in equalizers, timing recovery and system identification Proficiency in DSP concepts and applications Familiarity with mixed-signal modeling in Python/MATLAB/C/C++ Experience in system design and performance tradeoff Familiarity with simulation tools for analog, digital, and/ or mixed-signal circuits Familiarity with Machine Learning concepts Experience in firmware or embedded software development is a plus

Pre Venta de Ciberseguridad | Ingram Micro Chile Santiago, Chile posted: Posted 30+ Days Ago

Logic Design Engineer 2 Locations Job Description Meet the Team Join the Cisco Silicon One Front-End Design team, at the core of Cisco's silicon development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation. We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of what's possible. Cisco Silicon One™ is transforming the industry with a unified, programmable architecture powering Cisco's future routing portfolio and shaping the Internet for decades to come. Your Impact · Write and review micro-architecture specifications · Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements · Contribute to full chip integration, timing methodology, and analysis · Collaborate with verification engineers to resolve bugs and achieve coverage closure · Work with the physical design team to close timing and PnR issues · Support design methodology evolution and best practices · Perform debug, root-cause analysis, and post-silicon validation in the lab Minimum Qualifications · B.Sc./M.Sc. in Electrical Engineering from a top university · 6+ years of experience in a relevant field · RTL design experience · Familiarity with UVM and functional verification methodologies Preferred Qualifications · Experience with MATLAB simulations and bit-exact modeling environments · Familiarity with mixed-signal systems and environments · Knowledge and hands-on experience with Clock Domain Crossing (CDC) Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years

Advanced DRAM Process Integration Engineer Boise, ID - Main Site posted: Posted 30+ Days Ago

CPU Cache Microarchitect/RTL Engineer Beaverton, United States of America Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products! Apple's Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that power our innovative products, including the iPhone, iPad, Watch, Vision Pro, and Mac. We are looking for an experienced engineer who can drive CPU multi-level cache subsystem architecture and RTL development for multi-processor systems. As a CPU Cache Microarchitect/RTL Engineer, you will own or participate in the following: • Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification • RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification • Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance • Design

ASIC Design Engineer Edinburgh, Scotland, United Kingdom AST SpaceMobile is building the first and only global cellular broadband network in space to operate directly with standard, unmodified mobile devices based on our extensive IP and patent portfolio and designed for both commercial and government applications. Our engineers and space scientists are on a mission to eliminate the connectivity gaps faced by today's five billion mobile subscribers and finally bring broadband to the billions who remain unconnected. Position Overview We are seeking an ASIC Design Engineer to contribute to the design and implementation of complex silicon solutions used in AST's space‑based communications systems. The Silicon Team in Edinburgh is a small, highly focused group responsible for developing high‑value silicon that is core to AST's mission of “Connecting the unconnected” - delivering the world's first space‑based mobile broadband network. The team works collaboratively to define and build next‑generation silicon, exploring advanced silicon technologies to continuously improve performance, capability, and efficiency. This is a hands‑on environment where silicon decisions directly impact AST's ability to deliver a global communications network from space. In this role, you will focus on high‑quality RTL development, micro‑architecture definition, and close collaboration across engineering disciplines. You will work alongside architecture, verification, and system teams-both internal and external-to deliver robust, high‑performance ASIC and SoC designs from concept through tape‑out. Key Responsibilities: • Create high‑quality micro‑architecture specifications and RTL code. • Contribute to SoC integration and subsystem development. • Work with internal and external stakeholders, including architecture, verification, and software teams.

Custom Silicon Management Analog Design Lead - Sensors Austin, United States of America Are you a leader? Do you want to utilize your engineering background to make big things happen? Can you influence, connect, get results and communicate effectively? Can you deliver on a predictable and dynamic schedule? We have an extraordinary opportunity for senior level engineers to drive and lead technical engagements between Apple and silicon and IP suppliers working on groundbreaking technologies. The Custom Silicon Management Group provides critical custom silicon for all mobile products including iPhone, iPad, iPod, and AppleTV. As an Analog Design Lead, you will work with multi-functional teams and external vendors to define, develop and productize the next generation of sensor solutions. Working with the Systems and Platform teams to establish silicon requirements - Touch, Optical, Motion and Health sensors Leading efforts to develop, integrate, characterize, and test silicon. Delivering first revision production worthy silicon per system requirements, on schedule. Driving continuous improvements in analog design methodology to achieve high quality first silicon. Working collaboratively with vendors to manage the development of new process technologies and next-generation architectures and circuit designs. Ensuring designs are properly verified, validated, and tested for long-term reliability. Managing schedules and supporting multi-functional engineering efforts. Minimum Qualifications: BS degree. Experience designing key analog blocks such as current mirrors, high resolution DAC, high resolution ADC, Phase Locked Loops, Delay Locked Loops, Oscillators, Trans-Impedance Amplifiers, or LDOs. Preferred Qualifications: MS degree and 10+years relevant industry experience. Experience taking projects from the concept