Stmicroelectronics jobs

Sr Principal Electronics Engineer - Network Engineer United States-California-San Diego

Sr Engineer, Physical Design Noida, , India Company Description: Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world's leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what's next in electronics and the world. Job Description: Experience: 5+ years Role Summary We are seeking skilled Physical Design Engineer with exposure of physical design cycle including Synthesis, UPF, VCLP, LEC to join our semiconductor backend team. The role focuses on performing RTL synthesis , LEC closure, UPF development, and VCLP analysis for complex SoC designs, working closely with Physical

Digital IC Design Engineer Austin, Texas, United States; Fremont, California, United States About Neuralink: We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. Job Description & Responsibilities: Our Digital IC Design Engineer will be responsible for delivering micro-architecture and register-transfer level (RTL) implementation of digital IPs and systems with a focus in high-throughput low-power digital signal processor (DSP) and general-purpose hardware accelerators towards realizing state-of-the-art brain-computer interfaces. Relevant product development experience in micro-architecture design for low-power processors, on-chip bus and network interfaces, audio/video compression processors, AI/ML accelerators, and communication PHY/MAC will be preferred. - Micro-architecture design and RTL implementation of: - Low-power digital signal processors - Low-power general-purpose hardware accelerators - Low-power graphics processing units - Low-power radio MAC/PHY - Low-power serial link MAC/PHY - Design and optimization of hardware/software interface with firmware engineers - Application-specific architecture optimization including: - Complex system modeling for energy and performance benchmarks - Workload analysis and modeling - Energy/performance profiling and analysis - Leveraging architecture-level design trade-offs with process technology and workload type - Balancing cost and performance

Senior Equipment Engineer Raider AMAT process – 2026 Singapore

Senior STA CAD/Methodology Engineer Armenia This is a hybrid role with four days per week at Cisco's Yerevan office. Meet the Team Join the Silicon One Team at Cisco, a group at the forefront of developing Cisco's groundbreaking silicon architecture. We are a collaborative unit focused on pushing the boundaries of ASIC design for advanced process nodes. As part of our team, you will contribute to defining innovative Physical Design methodologies and creating robust flows essential for developing our complex chips. You will also have the opportunity to work hands-on with the Physical Design of intricate chip partitions. Your Impact This role as a Static Timing Analysis (STA) CAD/Methodology Engineer on Cisco's Silicon One Engineering team offers a key opportunity to enable the next generation of high-performance networking SoCs and ASICs. You will lead the development of scalable STA flows and automation, enhancing the efficiency and quality of design processes. Working at the intersection of design, methodology, and infrastructure, you will help establish best practices and drive innovation within a leading silicon organization. Architect, develop, and maintain static timing analysis (STA) methodologies and flows to support full-chip and hierarchical signoff for high-speed networking ASICs. Support timing closure for SoCs with complex clocking structures, high-speed interfaces, and large-scale integration. Develop robust SDC management, checking, and validation infrastructure across multi-mode, multi-corner (MMMC) scenarios. Build and optimize automation scripts and infrastructure (TCL, Python, Makefiles, etc.) to scale timing flows for enterprise-level SoC programs. Collaborate with RTL design, DFT, P&R, and signoff teams to

ALTERNANCE - Système de Management Qualité - F/H Rousset, France

Sr. Staff System & Application Engineer – Power Electronics Plano, TEXAS, United States Company Description: As a System & Application Engineer, you will define and validate system-level solutions for server power products in the growing AI server market. In this hardware system engineering role, you will interface with customers and define power products and its specifications, generate validation plans, and reference designs to ensure robust integration in server, telecom, and industrial systems. You will be the one driving all the other functional teams to develop differentiated products for the target markets. Job Description: · Market survey and definition of power products and specifications for server power market. · Collaborate with customers, sales, product line marketing, applications, design and validation engineers to define architecture and specifications. · Benchmark existing solutions to understand the state of the art. · Silicon bring up and testing of key system performance parameters. · Design and develop proof-of-concepts and reference designs of power solutions for server market. · Develop calculators, simulation models, datasheet for releasing new products to market. · Perform system-level analysis for power integrity, thermal performance, and fault response. · Create application notes and reference designs demonstrating new products in real-world use cases. · Support customers and internal teams with design reviews and debugging for product adoption. Qualifications: · Masters/PhD in Electrical or Electronics engineering with 10+ years experience · Strong expertise in power electronics including DC-DC converters. · Hands-on experience with PCB schematics/layout and CAD tools. · Expertise in control theory and feedback

Sr Principal Electronics Engineer - Payloads United States-California-San Diego

STAGE Césure - Ingénieur Machine Learning - H/F Crolles, France

ALTERNANCE - Data Analyst automation & reporting F/H Grenoble, France

Senior Engineer - Assembly Process Engineering Calamba, Philippines | Philippines

Analog IC Layout Engineer Fremont, California, United States About Neuralink: We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. Job Description and Responsibilities: We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology. The ideal candidates are energetic people who get excited about building things, are highly analytical, and enjoy tackling new problems. You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team. As an Analog IC Layout Engineer, your responsibilities will include: - Crafting state-of-the-art layouts for mixed-signal and analog circuits - Amplifiers - Filters - Switched capacitor circuits - Oscillators - Data converters - Power management circuits - Reviewing layout floorplans and analyzing high-fidelity circuits with circuit engineers - Physical verification of custom IC mask layouts (LVS,

ALTERNANCE - Technicien de maintenance CVD/PVD - F/H Rousset, France

Sr. Technical Staff Sunnyvale, CA Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras , to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. Cerebras Systems Inc. has multiple openings for Sr. Technical Staff. Title: Sr. Technical Staff Job Duties: - Post silicon validation of Cerebras Wafer Scale Engines. Test and debug issues on new silicon. - Test, analyze, and characterize high-speed serial interfaces to verify compliance with hardware specifications, record performance data, and recommend design modifications to optimize functionality. - Work with the silicon and operations team to test, bring-up and run burn-in on wafers scale systems. - Support manufacturing operations to utilize the wafer bring up flow. Perform wafer

Deep learning Engineer Greater Noida, India | Bangalore, India

Sr. Power Supply Engineer (27443) US - HQ (US001) | Country United States | State California | City San Jose Job Req ID: 27443 About Supermicro: Supermicro® is a Top Tier provider of advanced server, storage, and networking solutions for Data Center, Cloud Computing, Enterprise IT, Hadoop/ Big Data, Hyperscale, HPC and IoT/Embedded customers worldwide. We are the #5 fastest growing company among the Silicon Valley Top 50 technology firms. Our unprecedented global expansion has provided us with the opportunity to offer a large number of new positions to the technology community. We seek talented, passionate, and committed engineers, technologists, and business leaders to join us. Job Summary: Why This Role Matters Server power supplies are a cornerstone of data center reliability and efficiency. As data center demands grow for higher performance and energy efficiency, this role ensures Supermicro delivers advanced power supply solutions that meet rigorous quality and performance standards. Your leadership and technical expertise will directly impact Supermicro's ability to scale innovation and maintain its competitive edge in the server solutions market. Essential Duties and Responsibilities: What You'll Do Design and develop high-power, high-efficiency, and high-density AC/DC power supplies. Create and optimize high-efficiency, high-density DC/DC converters. Develop and validate power shelves and rack power test systems. Lead design reviews for new projects, ensuring robust and scalable designs. Drive performance and quality improvements for existing projects. Conduct second-source

Senior Digital Design Engineer (f/m/d) Dresden, , Germany Company Description: Renesas is a global leader in microcontrollers, analog, power, and SoC products. Our Development Team in Dresden/Munich designs the next generation of ASSPs for automotive and industrial sensing solutions. We are looking for a highly skilled and motivated Staff Digital Design Engineer to join our team and contribute significantly to our success in developing cutting-edge semiconductor products. Job Description: As a Senior Digital Design Engineer (f/m/d), you will play a crucial role in the design, development, and validation of digital modules for our sensing solutions. You will work closely with our System Engineer, Chip Architect, as well as with Analog, Digital, Verification, and Validation Engineers. Your expertise in RTL design and simulation will be pivotal in driving our projects to success. The Job Design, develop, and validate digital modules for automotive and industrial applications Extract digital module objectives from high-level specifications Take ownership of digital block implementation, ensuring robust and reliable design Perform RTL coding and debugging using Verilog and/or System Verilog Conduct RTL and gate level simulations to ensure design accuracy and performance Support product development deliverables, including DfT/DfM, design documentation Work closely with cross-functional teams, including analog design, verification, and DFT, to ensure cohesive project development Evaluate third-party IPs, customize, and integrate them into the design Qualifications: Your Profile A Bachelor's degree in Electrical Engineering, Electronics, Information Technology, or a related field 4+ years of experience in digital design and analog/mixed-signal IC development Excellent knowledge in Verilog and

Sr. Hardware Design Engineer - x86 / GPU / HPC (27752) US - HQ (US001) | Country United States | State California | City San Jose Job Req ID: 27752 About Supermicro: Supermicro® is a Top Tier provider of advanced server, storage, and networking solutions for Data Center, Cloud Computing, Enterprise IT, Hadoop/ Big Data, Hyperscale, HPC and IoT/Embedded customers worldwide. We are the #5 fastest growing company among the Silicon Valley Top 50 technology firms. Our unprecedented global expansion has provided us with the opportunity to offer a large number of new positions to the technology community. We seek talented, passionate, and committed engineers, technologists, and business leaders to join us. Job Summary: As a global leader in networking solution innovation, Super Micro Computer's mission is to develop and provide the market with end-to end computing solution and high performance networking products. We have an immediate need for a Sr. Hardware Design Engineer to join our talented and bright design team. The candidate will play a key role in the development process of in-house server motherboards, by working collaboratively with cross-functional engineering team as well as outside partners to ensure the robust design of the boards. The candidate must be self-motivated and possess a strong will to do great things, with a result-driven mindset to develop the most competitive and endurance board products. Essential Duties and Responsibilities: Lead schematic capture, layout review, BOM generation, debugging, and testing for server motherboards, add-on cards, and backplane products. Collaborate close

HR Manager - Learning, Development and Talent Acquisition Muar, Malaysia

Lead MTS Physical Design/STA Bangalore, KA, IN Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Lead Static Timing Analysis Engineer to join our STA team in Bangalore. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Responsibilities Complete ownership of Static timing analysis at full chip level for high speed mixed signal design Experience doing multi-mode multi-corner (MMMC) timing and power analysis using primetime/Tempus. Experience in DMSA/Tweaker ECO flows for PPA improvements. Experience in manual timing fixes, ECO generation for MCMM mode corners. Good understanding of SDC constraints and able to translate timing requirements into constraints. Responsible for integrating the blocks, analog Ip's for full chip timing analysis. Well aware of place and route methodologies and hands on experience with timing convergence Good communication skill to negotiate with top level for convergence. Work closely with Project leader for creating schedule, tracking and raising issues / risks to project management. Participate in Mentoring new joiners in the group on technical skills. Provide inputs for CAD/DA team from Design Implementation perspective. Work closely with Logic design team and Analog teams to provide inputs from physical design and STA. Work closely with DFT team on scan aspects and provide inputs from physical design. Continuously work on methodology and productivity improvements. Qualifications Must have at least 10 - 12 years of experience, out of which

Technical NPI Engineer-Assembling Hsinchu City, Taiwan

PCB Layout Engineer San Jose, CA, United States About Etched Etched is building the world's first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary We're seeking a skilled PCB Layout Engineer to join our dynamic team and contribute to our high-performance data center products. As a PCB Layout Engineer at Etched, you will play a crucial role in designing and optimizing printed circuit boards (PCBs) using Cadence Allegro PCB design tools. Your primary focus will be on high-speed signaling, including 100G applications, power distribution, large BGA ball-map breakouts and complex HDI PCB stack-ups for high-performance data center products. Your expertise will ensure that our products meet the highest standards of performance, reliability, and efficiency. Key Responsibilities - Lead the design and optimization of high-speed PCB layouts using Cadence Allegro, tailored for 100G signaling. Implement strategies for impedance matching, trace routing, and crosstalk mitigation, resulting in robust designs that meet the stringent performance demands of modern data centers. - Develop and implement power distribution networks for cutting-edge data center hardware. Design power planes, decoupling strategies, and thermal management solutions to support high-performance systems, ensuring

CDI - Ingénieur.e Maintenance Industrielle F/H Rousset, France

Electronics Engineer San Francisco, CA Electronics Engineer