Programmable Logic (PL) Engineer
Viasat INC - Carlsbad, California
Posted Apr 9, 2026
Benefits
- Parental leave
- Not verified
- Non-birth-parent leave
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- Family-building benefits
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- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
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- Relocation assistance
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- Childcare support
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- Learning budget
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- Verification
- Not verified last checked Jun 13, 2026
- Salary
- Not verified not verified - source not recorded; timestamp not recorded
- 401(k) match
- Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.
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Schedule
- Shift type
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- Weekend work
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Application
- Cover letter
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- Assessment
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- Deadline
- Not stated
Where they hire
State eligibility is not yet verified.
About this role
Programmable Logic (PL) Engineer Carlsbad, California About us One team. Global challenges. Infinite opportunities. At Viasat, we're on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate. We're looking for people who think big, act fearlessly, and create an inclusive environment that drives positive impact to join our team. What you'll do In this role you will help develop high speed signal processing algorithms, cryptography, and/or network protocols in FPGAs. The individual will be responsible for the full design phase starting from the requirements phase to documentation, block diagrams, implementation of source code, simulation, place & route, testing in hardware, and integration. The individual will collaborate with other engineers from different fields and must be capable of working in both a small team setting and a larger team setting. Experience in the development of high-performance FPGA designs, network encryptors and cryptographic devices is a plus. The day-to-day Design FPGA module and system level architectures with Verilog and/or VHDL Develop simulations for modules and systems Synthesizes Verilog and/or VHDL to FPGA products Develop timing constraints, analyze timing results, and implement design changes required to close timing Generate and collaborate on required design documents, development requirements, specifications and verification protocols Work closely with hardware and hardware engineers, bringing up boards, interpreting data sheets and schematics Conduct code and design reviews and participate in multi-functional reviews Maintain and control FPGA code
Read the full description at careers-viasat.icims.com. FewerJobs shows a source-linked preview and links to the original posting.
Apply link verified; last checked Jun 13, 2026.
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